missing nodes when using signaltap

[Altera_Forum]

When I use SignalTap for debugging, I find that not all the pins or registers in the designed program (write by verilog language ) always appear in the 'add notes' list. 

  The problem is that I cannot find some significant registers/pins sometime,do you have the same trouble ?   What should I do to avoid this situation ? Is this have something to do with the "post-synthesis" ? But the use of the 'pre-synthesis ' nodes is also not allowed!    Thanks for your replies!

[Altera_Forum]

I would try to avoid adding pins in signaltap. You're basically adding another register, which won't be in the IO cell, to capture the data coming in/out. I've seen users have timing problems with this, but since they don't have constraints, they don't know. If you use IO registers, it is probably better to tap those inside the FPGA fabric(i.e. tap after input registers, and before output registers.).  

For internal registers, they generally should be there, but no guarantees. They can be: a) Merged with other registers that have identical behavior b) Changed by Netlist Optimizations c) Changed by Physical Synthesis d) Probably a handful of other optimizations All of these are generally good things that make your design smaller and faster, it just makes finding nodes more difficult. You could turn off Assignments -> Settings -> Analysis & Synthesis -> More Settings -> Remove Duplicate Registers. Also don't have any Assignments -> Settings -> Netlist Optimizations/Physical Synthesis options checked, although both of these help timing so you may need them.  Finally, pre-synthesis should be acceptable, but anything you tap here will usually require a complete re-compile of your design, so it's much more convenient, but there's a trade-off. I tend to grab everything I want pre-synthesis and let it run overnight. If I want to do a quick test during the day, then choose the regular signaltap filter and accept that there will be some limitations.