Default drive strengths for Stratix III and Cyclone III

[Altera_Forum]

Note that Stratix III and Cyclone III default drive strengths on most I/O standards are set to OCT Rs for better signal integrity. On previous families they were set to max drive strength for best performance. This will change your I/O timing but will definitely improve your signal integrity.

[Altera_Forum]

I'm playing dumb here, but what is OCT Rs? Shouldn't it be 4 mA or something like that. What is the drive for OCT Rs?

[Altera_Forum]

OCT Rs is the series on-chip termination setting. It gives a drive strength so that the output impedance of the buffer is close to 50ohms. This reduced overshoot, etc, making signal integrity better. The actual drive strengths vary depending on IO standard. You can calculate the OCT Rs drive strength for a given IO standard by using the I-V curve from the IBIS model.

[Altera_Forum]

Tanks for the help :D

[Altera_Forum]

I'm not convinced this is the best idea, I agree that this solution is better than the previous setting of MAX drive strength but: 

1) We are assuming a 50ohm scheme. 2) I believe that a default setting of MIN drive strength would be better as:   A) No matter how badly anyone lays out their PCB, this will result in the least overshoot / ringing etc and hence will cause the least electrical stress on the other devices on the board. B) Min drive strength would probably result in most designs NOT just working like magic, and hence would result in engineers actually thinking about the optimum drive strength setting for their system.

[Altera_Forum]

If you set min drive strength as default, you could violate timing at your receiver or underdrive your transmission line and end up not recognizing 1's/0's at the receiver. Not good. 

 I would rather have things work by default than having to think about everything. If Altera can provide me with "likely to work" settings, I'll take it. Then I can focus my debug and engineering time on the problems instead of having to check every little thing. Nowadays these chips are too complicated to do that.   Also, the vast majority of designers use 50ohm transmission lines, so setting the default to 50ohm makes sense.

[Altera_Forum]

Signal integrity problems are very difficult to debug. A "likely to work" scenario is a little scary. I have started using signal integrity analysis tools like hyperlynx and this has helped me to discover potential problems in advance. This way I can tune my drive strength based on my board abd IO characteristics. 

 Have you looked at tools like this to decide the best drive strength to use?  FPGA Guy

[Altera_Forum]

Yeah, Hyperlynx sims are the best way to go if you can do them. I try to use them whenever possible because it gives you the most accurate results since it takes into account your actual board topology and loading, etc.

[Altera_Forum]

Using OCT-Rs with 50ohm impedance assumption makes a lot of designs "most likely to work", instead of "likely to work". It has a better chance than using min drive strength because min makes the transition time too slow for some cases. If the default is MIN, the system probably will not work. And not everyone can afford tools to simulate and analzye SI.

[Altera_Forum]

Hi, 

 If you are interested in quickly looking into your I/O signal integrity but don't know how or don't want to run IBIS/HSPICE, you can use the Advanced I/O Timing feature of Quartus II. You must turn it on for Stratix II, and it is on by default for Stratix III in QII 7.1. Advanced I/O Timing allows you to specify a simple model of the outside world -- near- and far-end termination and loads, plus a transmission line -- and will compute various statistics. These stats include delay, ringing, slew rates, etc.  Quartus II can also help you with third party tools by writing out IBIS- and HSPICE netlists for your I/Os. The benefit of going this route (vs. setting up yourself) is that Quartus worries about the details (I/O standard, drive strength, voltages, measurement points) so you don't have to. And the resulting HSPICE decks are nicely commented so that you can muck with them to adjust to your needs.  Please see the I/O Management Chapter of the Quartus Handbook for details of using these features (http://www.altera.com/literature/hb/qts/qts_qii52013.pdf)).  Paul Leventis Altera Corp.