Re: Verilog

Altera_Forum · ‎03-24-2006

Hello;

I am working on Altera's NiosII development kit (Cyclone Edition).Whenever I tried to run my verilog program the board's error LED blinks and the default factory written program starts runing.

These are my steps:

I write program e.g adder-subtractor in verilog.

Then compile it in Quartus II

Then i open the programmer tool and add my projects sof file

Click on Start.

The board waits for some seconds and then run its default program

I don't know whats the problem and how to solve it

Please help me.

Thanks

Altera_Forum · ‎03-24-2006

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originally posted by basheer@Mar 24 2006, 08:50 AM

hello;

i am working on altera's niosii development kit (cyclone edition).whenever i tried to run my verilog program the board's error led blinks and the default factory written program starts runing.

these are my steps:

i write program e.g adder-subtractor in verilog.

then compile it in quartus ii

then i open the programmer tool and add my projects sof file

click on start.

the board waits for some seconds and then run its default program

i don't know whats the problem and how to solve it

please help me.

thanks

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--- quote end ---

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Have you set reserve all unused pins "as input tri-stated" in Device assignments -> device & pin options -> unused pins?

The default value is output driving ground, this doesn't work for cyclone.

Altera_Forum · ‎03-25-2006

It worked.

Thank u SOooooooooooooooooooooo Much.Now i am able to run my verilog program

Thanks once again.

Altera_Forum · ‎04-05-2006

I have encounted the same problem. Now I have solvded it. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif

Thank you Kelle Leo very much! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

Altera_Forum · ‎04-15-2006

This happens on the Nios II development boards because there is a pin that drives out of the FPGA to the CPLD on the board. This pin when pulled low tells the CPLD to reprogram the board (look at the full featured design for the reconfig_n pin). So if you don't use the pin and don't have unused I/O set to input tristate, after downloading the pin goes low and the CPLD re-downloads a new hardware image out of flash.

A side effect of this is if you flash program a design that causes this behavior you'll see the LEDs on your board flash on and off really fast (because you just created an never ending configuration loop). Not that I've ever done this ....... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif