u-boot on the nios2 eval baord

[Altera_Forum]

Has anyone ported u-boot to the NIOS2 eval board?

[Altera_Forum]

Hi fmcmurra, 

 Which evalutation board are you using? There are several "Nios II" eval boards.  Porting is quite simple ... so even if a port does not exist, you can usually just use an existing Nios II board configuration with a few nips 'n tucks to the config header file and have a working u-boot. See:  http://forum.niosforum.com/forum/index.php...indpost&p=13700 (http://forum.niosforum.com/forum/index.php?act=st&f=18&t=3571&hl=&view=findpost&p=13700)  Regards, --Scott

[Altera_Forum]

--- Quote Start ---  originally posted by smcnutt@Apr 13 2006, 11:50 AM hi fmcmurra,  which evalutation board are you using? there are several "nios ii" eval boards.  porting is quite simple ... so even if a port does not exist, you can usually just use an existing nios ii board configuration with a few nips &#39;n tucks to the config header file and have a working u-boot. see:  http://forum.niosforum.com/forum/index.php...indpost&p=13700 (http://forum.niosforum.com/forum/index.php?act=st&f=18&t=3571&hl=&view=findpost&p=13700)  regards, --scott <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14344)  --- quote end ---    --- Quote End ---    Hi Scott, I don&#39;t have a problem porting u-boot to the NIOS II eval. baord (I&#39;ve done at least a couple dozen ports for ppc,arm,mps,etc.). I just didn&#39;t want to do it if someone else has already.  I pulled the src tree from the psyent.com download area and compiled a couple of boards from the src trree. So my dev. enviornment appears to be ok.  Forgive me for being a noob to NIOS2, it won&#39;t be for long.:-) I was under the impression there was only one eval board for the NIOS2. The rest are called devleopment boards. the one I have is based on the epc12 (cyclone?).  I&#39;ve looked at the code in the u-boot source tree I downloaded form the above site, but none of them appear to be enabling the CFI flash driver (CFG_FLASH_CFI_DRIVER) is this correct?  The flash chips on my eval board are CFI compliant so I&#39;m going to use that instead of flash.c. Are there any problems with this CFI driver. The one in the regular u-boot tree works just fine so I&#39;m hoping this one does too.  Another question I have: Which board should I use for my port? Should I use one of the bords in the psyent or the altera board directory.  Like I said I&#39;m an old hand at Linux and u-boot (started when it was ppcboot) but I&#39;m new to the FPGA&#39;s. So please be gentle if I appear to be asking stupid questions.:-)

[Altera_Forum]

--- Quote Start ---  originally posted by smcnutt@Apr 13 2006, 11:50 AM hi fmcmurra,  which evalutation board are you using? there are several "nios ii" eval boards.  porting is quite simple ... so even if a port does not exist, you can usually just use an existing nios ii board configuration with a few nips &#39;n tucks to the config header file and have a working u-boot. see:  http://forum.niosforum.com/forum/index.php...indpost&p=13700 (http://forum.niosforum.com/forum/index.php?act=st&f=18&t=3571&hl=&view=findpost&p=13700)  regards, --scott <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14344)  --- quote end ---    --- Quote End ---    Hi Scott, Should I be using the offsets that are in the system.h file that&#39;s located in my project softaware subdirectory?

[Altera_Forum]

Hi fmcmurra, 

 > none of them appear to be enabling the CFI flash driver (CFG_FLASH_CFI_DRIVER) > is this correct?  Correct -- depending on the polling mechanism, there are some issues.  > The flash chips on my eval board are CFI compliant so I&#39;m going to use that > instead of flash.c. Are there any problems with this CFI driver.  The CFI driver doesn&#39;t have an problems per se, but depending on your geometry, the avalon bus and the CFI driver don&#39;t always "play well" together. See: http://forum.niosforum.com/forum/index.php...wtopic=2302&hl= (http://forum.niosforum.com/forum/index.php?showtopic=2302&hl=)  > The one in the regular u-boot tree works just fine so I&#39;m hoping this one does too.  See the reference above. Also ...  The sources from psyent are from the "regular" u-boot tree -- in fact, the sources from pysent are identical with the following exceptions:  - the pysent tree has patches applied to support Nios-II. Each and every one of the patches have been submitted to the u-boot project. However, they have not been applied to the main source tree yet. Wolfgang has unfortunately been _very_ slow in applying them -- they were submitted in August and are still waiting (Arrgghh!).  - the psyent tree contains some "nips &#39;n tucks" to eliminate compile time warnings and to account for compatibility issues in a cygwin environment (since that is the most common for Nios-II developers). However, the structure and flow of the code remains identical.  - the psyent tree has code for other processor architectures removed. This was done only to reduce the download size.  - the psyent tree is synchronized with the main project infrequently. If I don&#39;t hear any complaints, my motivation is limited ;-)  > Which board should I use for my port? Should I use one of the bords in the > psyent or the altera board directory.  Probably the altera board directory is best -- perhaps the 1c20.  > I&#39;m an old hand at Linux and u-boot (started when it was ppcboot) but I&#39;m new > to the FPGA&#39;s.   That makes you are a sight for sore eyes! ;-) I&#39;m an old ppcboot person myself -- did the original 440GP port (1st book E ... on Ebony) and a variety of board ports before moving to Nios-32 and Nios-II. I&#39;m glad you&#39;re participating on this forum -- I&#39;ll be glad to share whatever I have -- just shoot me a PM with any specifics.  > Should I be using the offsets that are in the system.h file that&#39;s located in my > project softaware subdirectory?  Yes ... use whatever the base addresses are from your hardware design.  Best Regards, --Scott  BTW: I would encourage anyone interested in u-boot for Nios-II to apply some pressure to the main u-boot project (via the mailing lists) -- patches should take no longer than a few months to be applied (given the limited scope/size of the project).

[Altera_Forum]

--- Quote Start ---  originally posted by smcnutt@Apr 14 2006, 08:04 AM hi fmcmurra,   > the one in the regular u-boot tree works just fine so i&#39;m hoping this one does too.  see the reference above. also ...  thanks scott, i think i&#39;ll just hardcode the flashinfo until i get the board up and then i&#39;ll work on the cfi stuff.  the sources from psyent are from the "regular" u-boot tree -- in fact, the sources from pysent are identical with the following exceptions:  good job pruning this down and getting it to compile under cygwin., that was a nontrivial  task.  probably the altera board directory is best -- perhaps the 1c20.  ok, that&#39;s the one i chose as a model. i have it ported over, compiled and loaded into ram, but for some reason it i don&#39;t get anything out of the uart (not jtag uart). i single steped through the code and it appears to be in the main loop waiting for input.  as you know the eval board doesn&#39;t have the _real_ uart connected. it comes out to a max232 and terminates at the pads on the proto area. i added a connector and wired it up to a db9 as a null modem. serial comm is childs play to me so i know i have it wired up correctly. is there something else i should be doing, besides enabling it in the config file? also, i noticed the other boards have the sram enabled. i looked at my system.h file and their is no mention of sram. is it safe to assume my fpga doesn&#39;t have sram? i&#39;m inclined to believe it does, but wasn&#39;t enabled. should i enable it?    best regards, --scott  btw: i would encourage anyone interested in u-boot for nios-ii to apply some pressure to the main u-boot project (via the mailing lists) -- patches should take no longer than a few months to be applied (given the limited scope/size of the project). <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14379)  --- quote end ---    --- Quote End ---    I&#39;ll ping Wolfgang and see what kind of response I get. The guy does a great job with u-boot, but he can be abrasive sometimes.:-)

[Altera_Forum]

This ddidn&#39;t get sent for some reason: 

Hi fmcmurra,   > The one in the regular u-boot tree works just fine so I&#39;m hoping this one does too.  See the reference above. Also ...  Thanks Scott, I think I&#39;ll just hardcode the flashinfo until I get the board up and then I&#39;ll work on the CFI stuff.  The sources from psyent are from the "regular" u-boot tree -- in fact, the sources from pysent are identical with the following exceptions:  Good job pruning this down and getting it to compile under Cygwin., that was a nontrivial task.  Probably the altera board directory is best -- perhaps the 1c20.  Ok, That&#39;s the one I chose as a model. I have it ported over, compiled and loaded into ram, but for some reason it I don&#39;t get anything out of the UART (not JTAG UART). I single steped through the code and it appears to be in the main loop waiting for input. As you know the eval board doesn&#39;t have the _real_ uart connected. It comes out to a MAX232 and terminates at the pads on the proto area. I added a connector and wired it up to a DB9 as a NULL modem. Serial comm is childs play to me so I know I have it wired up correctly. Is there something else I should be doing, besides enabling it in the config file? Also, I noticed the other boards have the SRAM enabled. I looked at my system.h file and their is no mention of SRAM. Is it safe to assume my FPGA doesn&#39;t have SRAM? I&#39;m inclined to believe it does, but wasn&#39;t enabled. Should I enable it?    Best Regards, --Scott  BTW: I would encourage anyone interested in u-boot for Nios-II to apply some

[Altera_Forum]

Hi fmcmurra, 

 > but for some reason it I don&#39;t get anything out of the UART (not JTAG UART). > I single steped through the code and it appears to be in the main loop waiting > for input.  Make sure your clock setting is correct (CONFIG_SYS_CLK_FREQ). For the &#39;standard&#39; FPGA configuration this should be 80 MHz (since the 24 MHz external clock is routed to a PLL). In the old versions of quartus, this was obvious since the PLL was always on the main schematic (bdf file). The new versions support the PLL component in SOPC Builder -- so it&#39;s real easy to overlook.  > Is there something else I should be doing, besides enabling it in the config file?  Not really -- I believe the baudrate is fixed at 115200 for the standard configuration. You can try switching to the jtag uart -- if that works, your problem will be isolated to uart1 ... if it doesn&#39;t, there&#39;s probably another problem.  > Is it safe to assume my FPGA doesn&#39;t have SRAM? I&#39;m inclined to believe it does, > but wasn&#39;t enabled. Should I enable it?  I don&#39;t think the eval board has any external SRAM. You can create an on chip RAM with SOPC Builder if you like. It looks like there&#39;s plenty of memory left in the standard configuration -- although it&#39;s not necessary for any of the Nios-II specific code in u-boot.  Regards, --Scott

[Altera_Forum]

--- Quote Start ---  originally posted by smcnutt@Apr 14 2006, 10:33 AM hi fmcmurra,  > but for some reason it i don&#39;t get anything out of the uart (not jtag uart). > i single steped through the code and it appears to be in the main loop waiting > for input.  make sure your clock setting is correct (config_sys_clk_freq). for the &#39;standard&#39; fpga configuration this should be 80 mhz (since the 24 mhz external clock is routed to a pll). in the old versions of quartus, this was obvious since the pll was always on the main schematic (bdf file). the new versions support the pll component in sopc builder -- so it&#39;s real easy to overlook.  > is there something else i should be doing, besides enabling it in the config file?  not really -- i believe the baudrate is fixed at 115200 for the standard configuration. you can try switching to the jtag uart -- if that works, your problem will be isolated to uart1 ... if it doesn&#39;t, there&#39;s probably another problem.  > is it safe to assume my fpga doesn&#39;t have sram? i&#39;m inclined to believe it does, > but wasn&#39;t enabled. should i enable it?  i don&#39;t think the eval board has any external sram. you can create an on chip ram with sopc builder if you like. it looks like there&#39;s plenty of memory left in the standard configuration -- although it&#39;s not necessary for any of the nios-ii specific code in u-boot.  regards, --scott <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14388)  --- quote end ---    --- Quote End ---     Got it! I had the clock set for 24MHZ. Are you sure it&#39;s 80MHZ. I seem to recal seeing 66MHZ in SOPC Builder.  If I didn&#39;t talk with you, how would I know to change the sys clk to 80MHZ. What other got ya&#39;s are there?  Even if the sys clk was wrong I would still expect to see some garbage coming out of the UART. I&#39;ll make the clock chnage and if that doesn&#39;t fix it, I&#39;ll get out the scope to see if anything is wiggling on the TX pin.  Thanks for the help...

[Altera_Forum]

> Are you sure it&#39;s 80MHZ. 

 The examples (version 5.1) show 80 MHz on my machine -- but I can&#39;t guarantee they haven&#39;t been changed.  > If I didn&#39;t talk with you, how would I know to change the sys clk to 80MHZ.  You can check the settings in SOPC Builder. In the System Contents tab you can view all defined clocks and associated frequecies. Enable &#39;View->Show Clock Source&#39; to identify the clock used for the component in question. You can double-click the pll component and open the MegaWizard for the details.  You can also open the ptf file and view the clock_freq settings for the system module -- this is handy if you prefer the quick &#39;n dirty ;-)  Regards, --Scott

[Altera_Forum]

> Are you sure it&#39;s 80MHZ. I seem to recal seeing 66MHZ in SOPC Builder.  

 Ok ... I&#39;ve been looking at the &#39;standard&#39; configuration ... which is 80 MHz. If you&#39;re using the &#39;full featured&#39; configuration, then 66 MHz is correct.  Regards, --Scott

[Altera_Forum]

--- Quote Start ---  originally posted by smcnutt@Apr 14 2006, 12:09 PM > are you sure it&#39;s 80mhz. i seem to recal seeing 66mhz in sopc builder.   ok ... i&#39;ve been looking at the &#39;standard&#39; configuration ... which is 80 mhz. if you&#39;re using the &#39;full featured&#39; configuration, then 66 mhz is correct.  regards, --scott <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14391)  --- quote end ---    --- Quote End ---    Thanks Scott for the reply, but I have one more question: Why would full feature use a 66MHZ clok and standard uses a 80MHZ clock? Does the number of functional blocks determine the clock speed and if so, why?

[Altera_Forum]

--- Quote Start ---  originally posted by smcnutt@Apr 14 2006, 12:09 PM > are you sure it&#39;s 80mhz. i seem to recal seeing 66mhz in sopc builder.   ok ... i&#39;ve been looking at the &#39;standard&#39; configuration ... which is 80 mhz. if you&#39;re using the &#39;full featured&#39; configuration, then 66 mhz is correct.  regards, --scott <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14391)  --- quote end ---    --- Quote End ---    Ok Scott, I have lift off, but only on the JTAG UART. Thanks for your help. Next task, get the _real_ UART working...

[Altera_Forum]

> Why would full feature use a 66MHZ clok and standard uses a 80MHZ clock? 

> Does the number of functional blocks determine the clock speed and if so, why?  As more "area" is consumed by your design, it becomes increasingly difficult to route signals through the available interconnect paths. When things get crowded, critical paths get longer and propagation delays increase -- so you have to slow down the clock to meet the required setup, hold, etc. times.  > I have lift off, but only on the JTAG UART.   Great!  Regards, --Scott