reconfig PLL in CycloneIII

[Altera_Forum]

hi everybody, 

 I'm using an EP3C10 and I have to reconfigure one pll. I've tried with the altpll_reconfig but i can't be able to use it properly.  Then I have made my own VHDL block to generate the scandata, scanclkena, and configupdate signals. These signals meets the altera requirements(fig 6-26 of the Cycl3-Handbook) but I only get the inclk0 at the outputs of my pll.  Do anyone know how I can do the real time reconfiguration for my pll?  tks

[Altera_Forum]

It's easiest to get your feet wet on PLL reconfiguration by using a MIF. Let Quartus II generate a MIF with your initial PLL settings. Then, open that MIF in a text editor. Don't open it in Quartus II, it only shows a matrix of numbers. If you open it in a text editor, you'll see all of the comments for where the parameters are at. Makes it easy to make adjustments. Change the counters on the C0 output and save the MIF. Compile your design, use the altpll_reconfig block with that MIF defined, pulse the reconfig port, and then see if the output clock changed according to your new factors you wrote to the MIF.  

 The altpll_reconfig takes care of all the timing and handshaking signals, it's tough to use the figures in the handbook since they are usually functional diagrams and not necessarily timing information. Perform timing simulation to get the real timing parameters.

[Altera_Forum]

Thank you Desert Rat, 

 It's very easy to use the altpll_reconfig in this way, and now my system works well.  Regards

[Altera_Forum]

Never mind...

[Altera_Forum]

Hi, 

 I have an other problem with the pll reconfiguration.  My FPGA is an EP3C16 and has 2 pll. Until now, I only reconfigure one pll but now, I'd like to reconfigure both. I have done the same thing to reconfigure the second pll but it doesn't go well.   The output of the pll are mixed, i-e if clk0 should become 24MHz and the 4 others 85MHz, after reconfiguration I have 4 clocks at 85MHz but the 24MHz one is clk 1... or clk3... or clk4... It changes at each compilation. Sometimes I only get clocks at 85MHz but it doesn't happen often.  I tried several way to perform the configuration : with one pll_reconf and several rom and with several pll_reconf but it doesn't change anything.  has anyone an idea to solve my problem? thanks!

[Altera_Forum]

--- Quote Start ---  The output of the pll are mixed, i-e if clk0 should become 24MHz and the 4 others 85MHz, after reconfiguration I have 4 clocks at 85MHz but the 24MHz one is clk 1... or clk3... or clk4... It changes at each compilation. Sometimes I only get clocks at 85MHz but it doesn't happen often.  --- Quote End ---  I have seen very similar results in one of my designs before. It seems when the fitter is optimizing, it sometimes chooses different PLL outputs than you actually specified in your design. If you check the PLL usage section in the fitter report, you can see how the outputs are mapped. I found I had to tweak my PLL reconfig data accordingly. Unfortunately, the mapping can change on subsequent compiles without warning messing it all up again. I never found a good way to deal with the problem. If you find a good work around or anyone else knows one, I would like to hear it.

[Altera_Forum]

hi, 

 I have solved my problem but I don't understand why it's solved and why it was there....  I just have made a new empty project in a new directory. I have copied all "vhd" and "bdf" files in this folder and I did "open" then "save as" with the same name in Quartus. Then I have recreated all "bsf" blocks. I have recreated all quartus component too i-e lpm_mux, lpm_dff, altpll, altsyncram... Now everythiong works, but I have no idea where my problem came from.