How to make a NULL FPGA (CycloneII) - a complete empty design

[Altera_Forum]

I am trying to make a FPGA design that behaves just like an unconfigured FPGA - from a boundary scan point of view. 

Why ? we test boards with Boundary scan ,and factory new boards with empty flash are never a problem,the FPGA is unconfigured and finds no valid code to configure. If we want to retest a board from the field,it comes with a programmed flash,and starts up immediately after power up.The active content of the FPGA (generally a NIOSII plus something) interferes with the boundary scan functionality. I can use the JTAG tools to reprogram the FPGA with something else (blow in a SVF file) that works fine,kills the NIOS,but afterwards the boundary scan cells are not behaving the same as with an unconfigured device.  In MAXII devices it works to make a design with all inputs (as many as the device has User I/O's) but now with a Cyclone II this trick doesnot work. I made a design like this : ------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity EP2C5Q208_null is  port (  signal GENIO : INOUT STD_LOGIC_VECTOR(131 downto 1);   signal GENIN : IN STD_LOGIC_VECTOR(8 downto 1)   );     end entity EP2C5Q208_null;  architecture RTL of EP2C5Q208_null is begin end RTL; ------------------------------------------------------------------- and even used the BSDL customizer,and tried to test the design with a modified BSDL file,but nothing seems to work. If you read Altera's AN039 document,it describes the boundary scan cell integration in the IO's but doesnot mention what heppens after configuration.

[Altera_Forum]

You didn't tell in which regard your empty design doesnt't work as expected.

[Altera_Forum]

Well it looks like the JTAG capture function isn't working properly. 

I have 18 test vektors,and the readback from vektor 2...17 is the same as of vektor 1. It should however read only 1 difference :the state of the nCONFIG pin.

[Altera_Forum]

May be the pins are driving out, cause you set them to inout without setting 'Z' output state. I did'nt understand, why you defined the port pins at all. They aren't needed for a blank design.  

 I have e. g. a blank SFL design, it uses no port pins (apart from internal defined ASMI pins). In this case, the ununsed pins setting has to be input tristated or similar. But I think, you could also force outputs in BSDL, so I don't actually understand, how BSDL functionality can be blocked by a configuration

[Altera_Forum]

Why can't the BSDLCustomizer works? You can just use your existing design and generate the new BSDL file with your PIN file. Use the new BSDL file for scan test. Make sure you don't pull your nConfig to low because that will loose your device configuration and the new BSDL file won't work then.

[Altera_Forum]

Well guys,thanks for thinking along with me. 

 I am a little further now. 1) assigning th pins to Z doesnot work.The pin file shows 'bidir' for the pins but if you go to the "chip planner" in Quartus,you'll see that the Output Enable is not connected. Quartus is too smart in this,whwnever it can it will optimize,an if it sees that the output is always or never enabeled,it will not even connect the output enable.   The following design works:   entity EP2C5Q208_null is  port (  signal GENIO : INOUT STD_LOGIC_VECTOR(131 downto 1);  signal GENIN : IN STD_LOGIC_VECTOR(7 downto 1);  signal TS : IN STD_LOGIC  );     end entity EP2C5Q208_null;  architecture RTL of EP2C5Q208_null is   begin  process(TS)  begin  if TS='0' then  GENIO <= "11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";  end if;  if TS='1' then  GENIO <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";  end if;  end process;   -------------------------------------------------------------------------- I can do boundary scan tests on it just like it were an empty chip (except for the TS line ofcoarse).The IO cells all have 3 connections if you look in the "chip planner" and click on some IO cell.I don't even need de BSDL customizer.   2)RUBIKIAN, to answer your thread : it just doesnot do what I expect. I think (now) that its main purpose is removing the LVDS assignments from being scannable.The cause of the boundary scan not testing correct lies in the fact that I/O cells must have 3 connections (DATAIN,OE and COMBOUT) in a configured device. At first I thought that unconfigured,or unused pins were removed from the scan chain in a configured device,rendering a shorter chain.But this is not the case.The scan cells are only changed in their behaviour,and the scan chain always has the same length,device being configured or not.

[Altera_Forum]

Yes, the scanchain is hardware wired and that is why it is not changed in length.  

 For LVDS, the N-pin is not connected to the IO pin while in Boundary Scan mode. The P-pin will behave like the usual IO pin. Therefore, you have to set the N-pin as untestable in the BSDL file by making it linkage pin and setting the behavior to untestable.