I write this code for 8 bit adder :
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--Use work.fulladd_package.all;
---------------------------------------------------------------------------
Entity fullAdder is
port(
Cin : in std_logic;
x : in std_logic;
y : in std_logic;
s : out std_logic;
Cout : out std_logic
);
end fullAdder;
Architecture fullAdder_logic of fullAdder is
begin
s <= x xor y xor Cin;
Cout <= (x and y) or (x and Cin) or (y and Cin);
end Architecture;
---------------------------------------------------------------------------
Entity eightBitAdder is
port(
Cin : in std_logic;
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(7 downto 0);
s : out std_logic_vector(7 downto 0);
Cout: out std_logic
);
end eightBitAdder;
Architecture eightBitAdder_logic of eightBitAdder is
component fullAdder
port(
Cin,x,y : in std_logic;
s,Cout : out std_logic
);
end component;
signal carry : std_logic_vector(8 downto 0);
begin
carry(0) <= Cin;
gen_add: for i in 0 to 7 generate
lebel_fulladd: fullAdder port map (carry(i), x(i), y(i), s(i), carry(i + 1));
end generate gen_add;
Cout <= carry(8);
end Architecture;
but it return this error:
Error (10482): VHDL error at PartI.vhd(29): object "std_logic" is used but not declared
