I have built a 8 bit custom component and I managed to write some firmware code to write and read via this interface. However when I tried to increase the readdata and writedata bits to 16 or 32 bits to make it into a 16 or 32 bit interface my write no longer seemed to work. My reads seem still to be fine. All I did was increase the my declaration of my signals in my VHDL code from
READdata :out std_logic_vector(7 downto 0);
WRITEdata :in std_logic_vector(7 downto 0);
to
READdata :out std_logic_vector(15 downto 0);
WRITEdata :in std_logic_vector(15 downto 0);
All other parts of the code I left unchanged. I tried different things but nothing seemed to work. I even added ByteEnable signals (which from the Altera Literature I didn't think I needed) but this didn't help.
Anyone have any suggestions ?
