Problem generating NIOS II .bsf - .vhd

[Altera_Forum]

Hello  

 I changend from Xilinx to Altera a few days ago. In that case I´m a newbie in Quartus. I´m using Quartus II 8.1 and I want to implement a NIOS II in my FPGA. SOPC Builder outputs 2 files I want to use - a .bsf and a .vhd. In my opinion these 2 files have to represent the same processor. But the .bsf has 2 ports in the schematic and the .vhd has many other ports from memory, uart and so on for input and output in the port list. What is wrong or how do I handle this, if I want to link the .vhd as a component in my top-entity?  I can´t let the other input ports open!?     Thanks for help, Christoph

[Altera_Forum]

In my experience w/ the Nios projects, I would use the .VHD file to grab the appropriate component declaration information (as well as for the instantiation), but then use the .sopc file in Quartus. If you look at the very bottom of the <project_name>.vhd for the Nios project, you'll find the declared module text. The following is the naming format for the Nios ports (named pio_in16 and pio_out16 in the SOPC project, respectively): 

 -- the_pio_in16 in_port_to_the_pio_in16 : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- the_pio_out16 out_port_from_the_pio_out16 : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);  I have found that the following assignments are all I need to get Nios working as an instantiation in a Quartus project.  [path] = location of the SOPC builder project "nios_project" = name of the Nios project  This also assumes that you are using on-chip memory for the codespace (which is what I do).  set_global_assignment -name SEARCH_PATH [path]  set_global_assignment -name SOURCE_FILE [path]/nios_project.sopc set_global_assignment -name QIP_FILE [path]/nios_project.qip  set_global_assignment -name VHDL_FILE [path]/onchip_memory_0.vhd set_global_assignment -name HEX_FILE [path]/onchip_memory_0.hex set_global_assignment -name MIF_FILE [path]/cpu_0_ociram_default_contents.mif set_global_assignment -name MIF_FILE [path]/cpu_0_rf_ram.mif  Jeff

[Altera_Forum]

the top level sopc verilog or vhdl file includes many modules/entities, only one of which is the top level. If you scroll all the way to the bottom of the file there is a test bench that includes the sopc system port declaration, you will find this matches the bsf. 

 --dalon