Re: SOPC builder - std_logic ports/signals must be width 1

Altera_Forum · ‎12-24-2008

I've got an SOPC builder custom component that I just added (called "ddr2_ctrl2" below). I'm getting an odd error when trying to generate the system:

Error: ddr2_ctrl2: Internal error: std_logic ports/signals must be width 1

Unfortunately, that's all it tells me. The ddr2_ctrl2 component synthesizes fine if I create a project with it as the top level entity. The declaration is below.

Does anyone have any suggestions to either

1) Get more info as to what is causing the problem from sopc builder? sopc_builder_log.txt is empty

2) What below might be causing the issue?

Thanks,

baver

entity ddr2 is

generic (

data_width : integer := 64;

burst_width: integer := 11

);

port (

-- inputs:

signal clock_source : IN STD_LOGIC;

signal global_reset_n : IN STD_LOGIC;

-- outputs:

signal mem_addr : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);

signal mem_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);

signal mem_cas_n : OUT STD_LOGIC;

signal mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

signal mem_clk : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);

signal mem_clk_n : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0);

signal mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

signal mem_dm : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

signal mem_dq : INOUT STD_LOGIC_VECTOR (63 DOWNTO 0);

signal mem_dqs : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);

signal mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

signal mem_ras_n : OUT STD_LOGIC;

signal mem_we_n : OUT STD_LOGIC;

signal memclk : out std_logic;

-- avalon bus

signal s1_read : in std_logic;

signal s1_write: in std_logic;

signal s1_address : in unsigned(24 downto 0);

signal s1_writedata : in std_logic_vector(data_width - 1 downto 0);

signal s1_readdata : out std_logic_vector(data_width - 1 downto 0);

signal s1_readdatavalid: out std_logic;

signal s1_burstcount : in unsigned(burst_width - 1 downto 0);

signal s1_beginbursttransfer: in std_logic;

signal s1_waitrequest: out std_logic;

signal s1_byteenable : in std_logic_vector(data_width / 8 - 1 downto 0)

);

end entity ddr2;

Altera_Forum · ‎12-24-2008

Apparently there were extra files in the component file list that were not actually used for the component. Removing these fixed the problem.

Altera_Forum · ‎01-23-2009

Hello,

I have the same problem but I haven't found a solution yet. I import my project from Quartus 7.2sp2 into Quartus 8.1 and then starts the SOPC generation. I don't have any problem with Quartus 7.2 but I get the error "std_logic ports/signals must be width 1" with Quartus 8.1. What did you do to solve the problem?

Thanks in advance for your help.

Altera_Forum · ‎02-11-2009

I am having a similar problem. Which files are causing it??

Thanks; JB