LUT hazards

[Altera_Forum]

Assuming only one input changes at a time, are LUT free from hazards?

[Altera_Forum]

In 2004, an authoritative source at Altera said, "The chips themselves guarantee that when a single input to a look-up table changes, the output will not glitch." This statement applied to all 4-input-LUT-based device families up through at least the original Stratix plus MAX II. I expect it is true for newer families with 4-input LUTs. I don't remember ever getting an answer about this specifically for families with ALUTs. 

 In the post at http://www.alteraforum.com/forum/showthread.php?p=7144, someone found an on-line solution that said more than one LUT input may change without a glitch on the output. I did not get a response from Altera when I asked if the solution is correct, but I have since then been told yet again by someone at Altera that you have to limit the number of changing inputs to just one changing input if you need to prevent glitches on a LUT output (like a LUT in a clock path or driving an asynchronous reset).

[Altera_Forum]

Thanks Brad, 

 It does make sense, and I expected, that a single change to the LUT input won't produce glitches in the output.  I don't quite understand the concept about multiple inputs changing at the same time, because two signals will never change exactly at the same time.

[Altera_Forum]

--- Quote Start ---  I don't quite understand the concept about multiple inputs changing at the same time, because two signals will never change exactly at the same time.  --- Quote End ---     To prevent glitches on the LUT output, you must not let more than one input change at approximately the same time. There isn't a spec or a timing report saying just how far apart in time toggles on two inputs must be to guarantee no glitch on the output. This doesn't matter for a synchronous design with the logic feeding a register.  More than one input toggling at about the same time matters for something like a latch where the data and enable must not change at about the same time for a D latch and the set and reset must not change at about the same time for an SR latch. There are in effect setup and hold requirements between the latch inputs, but Quartus doesn't analyze that timing.  More than one input toggling at about the same time matters for combinational logic that must not be allowed to glitch like a clock or an asynchronous reset. There are ways to avoid glitches in these applications without having to know how close in time two LUT inputs are allowed to toggle; see http://www.alteraforum.com/forum/showthread.php?p=8506#post8506.

[Altera_Forum]

Thanks again Brad. 

 That's quite interesting. In my case it's about an async reset, and not about a clock. In this case it is then ok as long as you have only two input signals, but it might be dangerous for more.  With only two inputs, if both happen to change at (about) the same time, then it means that the output would change even with an ideal LUT (that doesn't ever glitch). So you don't care.  But if you are combining 3 inputs where you want the async reset output to be active only when all the inputs are active, then you might get a glitch even when one of them was always inactive. Interesting.