test sram in nios ok,but sram can not be program memory

[Altera_Forum]

Hi everyone! I have a test program for sram like as follows:  alt_u16 *temp=SRAM_16BIT_512K_BASE; alt_u16 i=0; alt_u16 data[100]; int main(void) { for(i=100;i<200;i++) {  *(temp+i)=i; } temp=SRAM_16BIT_512K_BASE; for(i=100;i<200;i++) {  data=*(temp+i); } for(i=100;i<200;i++) {  printf("data[%d]==%d\n",i,data); } while(1) {} return 1; }  SRAM_16BIT_512K_BASE =0x80000  It is the address about sram in nios-system, The result show me that write sram and read sram is ok. I have also test it in debug module ,with step-in module I can see that memory of sram have been writeen ok. But when I set sram as program memory ,there are something wrong about it. Wrong information is :verified 0x80000 and 0x81f70 failed when I run it! So i wish someone can help me!!:confused: 

[Altera_Forum]

Did you connect the instruction bus?

[Altera_Forum]

Yes,now when my program is little,nios download ok and there is no verify failed infomation ,but the program can not run in it. 

Because in the program I use "printf()" function printf a "Hello!"information to ide_console. So do you have some advice to me?

[Altera_Forum]

Just for your information, your code may not actually test your sram. The Nios CPU has a data cache, and with only 100 16-bit accesses, it is probably all kept in the cache. 

In order to actually test the SRAM, you would need to either use the alt_remap_uncached() function to define your temp pointer, or use the IORD/WR macros to read/write the memory.

[Altera_Forum]

Thanks for your advice,and now my pll in the fpga does not work,does this means that the pll in the fpga has broken.(fpga works ok if i do not use pll)?

[Altera_Forum]

It's more likely that you have a problem on your board, such as a bad connection, or a bad configuration of the pll or pins, or problems with the pll power supply.

[Altera_Forum]

You mean that pll in the fpga couldn't break if other part is ok in fpga?

[Altera_Forum]

I have test that the power for pll is ok!

[Altera_Forum]

Yes, I think it is extremely unlikely that the pll part of the FPGA fails alone. The problem must come from somewhere else.

[Altera_Forum]

Except the power of Pll part has some problem,are there some other things may cause:confused: this ?

[Altera_Forum]

As I said, bad configuration, or i/o pin problem. 

Can you connect the pll output and "locked" signal to an i/o pin and check them with an oscilloscope?

[Altera_Forum]

I have test that pll output to a i/o pin and check them with oscilloscope ,but without output! If i did not use pll then output was OK!

[Altera_Forum]

what about the 'locked' output of the pll? 

Is your source clock connected to a dedicated pll input? Are you sure the pll is connected to the correct pins? Are you sure that the input frequency of the pll is the same one than your oscillator? Do you have any warnings from quartus when you compile your project? Can you try an empty project with just the pll?

[Altera_Forum]

Try to derive a new clk out from the pll using Altera Mega function Wizard in SOPC B:Take it out throug one I/O pin and check it on a scope