Tag: "agilex"

Top Taggers

User

Count

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

Terms of Use
*Trademarks
Cookies
Privacy
Supply Chain Transparency
Site Map

Agilex 7 Power Sequencing WITHIN a Power Group by RamoneC New User in Programmable Devices 06-05-2024 0 0	0	0
Ethernet IP Core for Agilex 5 E-Series by Nicole04 Beginner in FPGA Intellectual Property 05-30-2024 0 0	0	0
FMC connector on DK-DEV-AGF014EA dev kit? by roeekalinsky Valued Contributor I in FPGA, SoC, And CPLD Boards And Kits 05-28-2024 0 4	0	4
Agilex Triple Speed Ethernet tcl script error by SamJak New Contributor I in FPGA Intellectual Property 04-24-2024 0 14	0	14
Agilex 7 I-series EMIF toolkit conflicting results by colm Novice in FPGA Intellectual Property 04-03-2024 0 5	0	5
mipi max speed by kikoss New Contributor I in FPGA Intellectual Property 04-01-2024 0 3	0	3
E-tile Clock management by khagesh1010 Novice in Intel® Quartus® Prime Software 02-25-2024 0 5	0	5
External Memory Interface IP on Agilex. by Big_Al Novice in Intel® Quartus® Prime Software 02-06-2024 0 14	0	14
Internal Error when attempting to program Agilex 7 on Intel Development Kit by bwa555221 Novice in FPGA, SoC, And CPLD Boards And Kits 12-12-2023 0 8	0	8
TRACE Interface through FPGA on Intel's Agilex 7 device not outputting clock by Fdominguez Novice in Programmable Devices 11-27-2023 0 14	0	14
Maximum external DDR4 memory capacity supported by Agilex 7 M- and I-Series? by RRReed Beginner in Programmable Devices 10-31-2023 0 3	0	3
GPIO INTEL IP IN DDR MODE NOT ABLE TO FIT IN IO BANK OF AGILEX FPGA (AGFB012R24B2I3E) by sumanth1 Novice in Intel® Quartus® Prime Software 10-16-2023 0 2	0	2
Agilex F Tile HPS I2C and MDIO by user1232 Beginner in Programmable Devices 10-16-2023 0 2	0	2
Package and Thermal Model for AGILEX 5 serie D A5D025 by ydouard Novice in Programmable Devices 10-16-2023 0 3	0	3
TNT Consultation Request ID [3212] - Sequential Routing for Memory AGILEX by Christopher_Alvarez Employee in FPGA, SoC, And CPLD Boards And Kits 10-05-2023 0 3	0	3
Regarding the Intel Agilex series GPIO Banks IO standards by Maitry Novice in FPGA, SoC, And CPLD Boards And Kits 07-17-2023 0 4	0	4
Bad timings for MSGDMA IP on Agilex 7 FPGA by Mikhail_a Novice in FPGA Intellectual Property 06-26-2023 0 18	0	18
Device tree generation for Agilex SoC by Mikhail_a Novice in Intel® SoC FPGA Embedded Development Suite 06-22-2023 0 5	0	5
Intel Agilex® 7 FPGAs with R-Tile Deliver Industry-Leading Bandwidth for CPUs – Now in Production by Thomas_Schulte Employee in FPGA 05-22-2023 1 0	1	0
Reflow Process recommendations of FPGA Agilex (AGFB012R24B2I3E) by khagesh1010 Novice in Programmable Devices 05-21-2023 0 2	0	2
Accelerate Your oneAPI Workloads with Intel Agilex® 7 Devices on Intel® DevCloud by DuncanMackay Employee in FPGA 05-08-2023 0 0	0	0
Intel® Quartus® Prime Software 23.1 sports new features and IP including a new RISC-V proces by Joel_Aaron_Seely Employee in FPGA 04-10-2023 0 0	0	0
F-tile transceiver IP simulation by SDe_J New Contributor I in FPGA Intellectual Property 03-08-2023 0 12	0	12
Generating an Agilex per pin RLC IBIS (.ibs) file by sumanth1 Novice in Programmable Devices 03-07-2023 1 5	1	5
package drawing by khagesh Novice in Programmable Devices 03-02-2023 0 5	0	5