Search
Browse
Community
Register
Help
SKGR0
Beginner
Intel Community
About SKGR0
Activity Feed
Posted
Re: How to fix the timing violation with an IP (altera_mult_add)
on
Intel® Quartus® Prime Software
.
06-15-2020
03:44 AM
Posted
Re: How to fix the timing violation with an IP (altera_mult_add)
on
Intel® Quartus® Prime Software
.
06-09-2020
09:08 AM
Posted
Re: How to fix the timing violation with an IP (altera_mult_add)
on
Intel® Quartus® Prime Software
.
06-09-2020
06:32 AM
Posted
Re: How to fix the timing violation with an IP (altera_mult_add)
on
Intel® Quartus® Prime Software
.
05-28-2020
05:46 AM
Posted
How to fix the timing violation with an IP (altera_mult_add)
on
Intel® Quartus® Prime Software
.
05-27-2020
07:16 AM
Posted
Re: Timing requirements not met inspite of optimised design.
on
Intel® Quartus® Prime Software
.
05-27-2020
07:00 AM
Posted
How to install Quartus Prime standard 16.1.203 on Linux?
on
Intel® Quartus® Prime Software
.
04-29-2020
08:09 AM
Posted
Timing requirements not met inspite of optimised design.
on
Intel® Quartus® Prime Software
.
01-06-2020
06:16 AM
Posted
Re: DDR4 Memory Access with Tartget Device - Arria10
on
FPGA, SoC, And CPLD Boards And Kits
.
11-18-2019
05:14 AM
Posted
Re: DDR4 Memory Access with Tartget Device - Arria10
on
FPGA, SoC, And CPLD Boards And Kits
.
11-14-2019
10:19 AM
Posted
Re: DDR4 Memory Access with Tartget Device - Arria10
on
FPGA, SoC, And CPLD Boards And Kits
.
11-08-2019
06:11 AM
Posted
DDR4 Memory Access with Tartget Device - Arria10
on
FPGA, SoC, And CPLD Boards And Kits
.
11-07-2019
12:15 PM
Posted
Re: How does DDR4-2400 (I/O Clock as 1200MHz) achieve higher data rate of 2.4 GT/s when memory clock is only 300MHz and the data width is limited to 144 bits on an Arria10 device?
on
FPGA, SoC, And CPLD Boards And Kits
.
11-07-2019
10:08 AM
Posted
Re: How to implement "dual channel mode" to get effective bit width of 128bits while operating with DDR4 with Arria10 device?
on
FPGA, SoC, And CPLD Boards And Kits
.
11-07-2019
09:49 AM
Posted
If I have a DDR4 -2400 (64-DQ pins) , configuring read/write data bit width as 64 in single channel mode I would receive 128bit data on request from DDR in a single clock Is my understanding correct?
on
FPGA, SoC, And CPLD Boards And Kits
.
11-06-2019
10:17 AM
Posted
How to implement "dual channel mode" to get effective bit width of 128bits while operating with DDR4 with Arria10 device?
on
FPGA, SoC, And CPLD Boards And Kits
.
11-06-2019
07:16 AM
Posted
How does DDR4-2400 (I/O Clock as 1200MHz) achieve higher data rate of 2.4 GT/s when memory clock is only 300MHz and the data width is limited to 144 bits on an Arria10 device?
on
FPGA, SoC, And CPLD Boards And Kits
.
11-06-2019
06:26 AM
Latest posts by SKGR0
Subject
Views
Posted
Re: How to fix the timing violation with an IP (altera_mult_add)
Intel® Quartus® Prime Software
95
06-15-2020
03:44 AM
Re: How to fix the timing violation with an IP (altera_mult_add)
Intel® Quartus® Prime Software
95
06-09-2020
09:08 AM
Re: How to fix the timing violation with an IP (altera_mult_add)
Intel® Quartus® Prime Software
95
06-09-2020
06:32 AM
Re: How to fix the timing violation with an IP (altera_mult_add)
Intel® Quartus® Prime Software
95
05-28-2020
05:46 AM
How to fix the timing violation with an IP (altera_mult_add)
Intel® Quartus® Prime Software
147
05-27-2020
07:16 AM
View all
Community Statistics
Posts
17
Solutions
0
Kudos given
0
Kudos received
0
Member Since
11-06-2019
