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JButt5
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Re: Custom Buildroot based Linux system for Cyclone V SoC fails to work with OpenCL RTE: "Board name /dev/acl0 is not available"
.
06-23-2020
01:23 AM
Posted
Re: Getting a lot of "HAL Kern Error: Read failed from addr x, read y expected z" errors – what to do?
on
Intel® High Level Design
.
11-25-2019
08:37 AM
Posted
Re: Getting a lot of "HAL Kern Error: Read failed from addr x, read y expected z" errors – what to do?
on
Intel® High Level Design
.
11-23-2019
10:53 AM
Posted
Getting a lot of "HAL Kern Error: Read failed from addr x, read y expected z" errors – what to do?
on
Intel® High Level Design
.
11-22-2019
04:36 PM
Tagged
Getting a lot of "HAL Kern Error: Read failed from addr x, read y expected z" errors – what to do?
on
Intel® High Level Design
.
11-22-2019
04:36 PM
Posted
Re: Repeated CL kernel invocation hangs after some successful runs during clFinish
on
Intel® High Level Design
.
11-22-2019
04:09 PM
Posted
Re: Repeated CL kernel invocation hangs after some successful runs during clFinish
on
Intel® High Level Design
.
09-18-2019
12:16 PM
Posted
Repeated CL kernel invocation hangs after some successful runs during clFinish
on
Intel® High Level Design
.
09-17-2019
07:10 PM
Posted
Re: Unexpected low Kernel Clock Frequency
on
Intel® High Level Design
.
09-14-2019
10:04 AM
Posted
Unexpected low Kernel Clock Frequency
on
Intel® High Level Design
.
09-11-2019
10:14 AM
Posted
Re: Error after first successful run of OpenCL application: acl_hal_mmd.c:1393:assert failure: Failed to initialize kernel interface
on
Intel® High Level Design
.
09-11-2019
10:00 AM
Posted
Error after first successful run of OpenCL application: acl_hal_mmd.c:1393:assert failure: Failed to initialize kernel interface
on
Intel® High Level Design
.
07-18-2019
10:19 AM
Posted
Re: Custom Buildroot based Linux system for Cyclone V SoC fails to work with OpenCL RTE: "Board name /dev/acl0 is not available"
on
Intel® High Level Design
.
06-13-2019
01:01 PM
Posted
Custom Buildroot based Linux system for Cyclone V SoC fails to work with OpenCL RTE: "Board name /dev/acl0 is not available"
on
Intel® High Level Design
.
06-03-2019
01:51 PM
Posted
Re: More up-to-date GCC for the Cyclone V SoC ARM available?
on
Intel® SoC FPGA Embedded Development Suite
.
05-21-2019
10:41 AM
Posted
More up-to-date GCC for the Cyclone V SoC ARM available?
on
Intel® SoC FPGA Embedded Development Suite
.
05-21-2019
09:23 AM
Posted
Wrong values when using CL_USE_HOST_PTR on a Cyclone V SoC
on
Intel® High Level Design
.
05-06-2019
10:20 AM
Latest posts by JButt5
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Views
Posted
Re: Getting a lot of "HAL Kern Error: Read failed from addr x, read y expected z" errors – what to do?
Intel® High Level Design
145
11-25-2019
08:37 AM
Re: Getting a lot of "HAL Kern Error: Read failed from addr x, read y expected z" errors – what to do?
Intel® High Level Design
145
11-23-2019
10:53 AM
Getting a lot of "HAL Kern Error: Read failed from addr x, read y expected z" errors – what to do?
Intel® High Level Design
422
11-22-2019
04:36 PM
Re: Repeated CL kernel invocation hangs after some successful runs during clFinish
Intel® High Level Design
67
11-22-2019
04:09 PM
Re: Repeated CL kernel invocation hangs after some successful runs during clFinish
Intel® High Level Design
67
09-18-2019
12:16 PM
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Member Since
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