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morca
Beginner
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HW counters for Haswell

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Where can I find information about the available HW counters in a Xeon v3 (Haswell)?

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McCalpinJohn
Black Belt
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The 0x10 event does not apply to the Xeon E5 v3 (Haswell) processors -- it was supported only on Nehalem/Westmere and SandyBridge/IvyBridge.  The events for Haswell are limited to those in sections 19.7 and 19.7.1

Intel has done a good job of keeping the tables at https://download.01.org/perfmon/ up-to-date.  These are separated by processor model and are a more convenient search target than the PDF documentation....

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McCalpinJohn
Black Belt
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The hardware performance counter events in the processor core in Intel processors are described in Chapter 19 of Volume 3 of the Intel Architectures Software Developer's Manual.  The Software Developer's Manuals can be found at https://software.intel.com/en-us/articles/intel-sdm

morca
Beginner
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Thanks. I see so many counters but I think vTune doesn't cover all of them. For example, I see

Event Num. = 10H

Umask Value = 01H

Event Mask Mnemonic = FP_COMP_OPS_EXE.X87

Description = Counts number of X87 uops executed.

But I can not find that in vTune configuration. Maybe I missed something in the configurations windows.

 

Dmitry_R_Intel1
Employee
140 Views

You can use INST_RETIRED.X87 event on Haswell. Should be available in VTune.

McCalpinJohn
Black Belt
141 Views

The 0x10 event does not apply to the Xeon E5 v3 (Haswell) processors -- it was supported only on Nehalem/Westmere and SandyBridge/IvyBridge.  The events for Haswell are limited to those in sections 19.7 and 19.7.1

Intel has done a good job of keeping the tables at https://download.01.org/perfmon/ up-to-date.  These are separated by processor model and are a more convenient search target than the PDF documentation....

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