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Hi,
I read some where in you site that when the distance between siblings in a structure is less than half the cache size, the chances of a cache hit are more. Can you please let me know the link?? I saw it in one of the flash slides..any reference to a paper is also appreciated
thanks
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Not sure what you are referring to. You can try the search mechanism. I found several interesting articles using it. For example, http://www.intel.com/cd/ids/developer/asmo-na/eng/20461.htm?page=2, which states:
"Typically, an application should target the block size to be approximately one-half to three-quarters of the cache size."
And, then, on the next page it states:
"In general, applications running on a Hyper-Threading Technology-enabled processor supporting two logical processors should target a cache block size of one-quarter to one-half the actual cache size of the physical processor."
So, that might be the reference you are talking about?
Regards,
Message Edited by DaveA on 10-05-2005 02:37 PM

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