I checked the three groups of preset-sampling-events in the analyzer for three architecture: Core, Nehalem and Sandy Bridge. The group I can use is Nelalem, does it mean that my processor belong to Nelalem Family?
But I used none of them , I used the non-preset group.
Just like the L2_LINES_IN.SELF.ANY , I Failed to find the CPU_CLK_UNHALTED.CORE event. So I selected all events start with CPU_CLK_UNHALTED, and here is one of my test reslut:
So, what's the difference between the CPU_CLK_UNHALTED*s ?
Yes, Xeon 5540 is a Nehalem CPU. If you meant what you seem to say about wanting L2 cache miss rate, you might simply add the L2 cache line miss retired event to the default events, no obvious reason why you would explore all the CPU_CLK events other than the one normally used. But maybe you don't mean L2 cache miss rate: L3 miss rate may be more significant if not as obvious how to collect.