How to measure FSB address bus utilization?

[ccuiyyan]

Hi All,

I want to measure the FSB address bus utilization to identify the bottleneck of

DB benchmark, there are lots of events in the event list, but i don't know which event

should be used. There is a server in my lab which is Xeon E5310.

All events are list here:

BUS_REQ_OUTSTANDING: (counter: all)
Outstanding cacheable data read bus requests duration (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_BNR_DRV: (counter: all)
Number of Bus Not Ready signals asserted (min count: 500)
Unit masks (default 0x0)
----------
0x00: this agent
0x20: include all agents
BUS_DRDY_CLOCKS: (counter: all)
Bus cycles when data is sent on the bus (min count: 500)
Unit masks (default 0x0)
----------
0x00: this agent
0x20: include all agents
BUS_LOCK_CLOCKS: (counter: all)
Bus cycles when a LOCK signal is asserted (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_DATA_RCV: (counter: all)
Bus cycles while processor receives data (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_BRD: (counter: all)
Burst read bus transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_RFO: (counter: all)
number of completed read for ownership transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_WB: (counter: all)
number of explicit writeback bus transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_IFETCH: (counter: all)
number of instruction fetch transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
&nbs p; 0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_INVAL: (counter: all)
number of invalidate transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_PWR: (counter: all)
number of partial write bus transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRANS_P: (counter: all)
number of partial bus transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRANS_IO: (counter: all)
number of I/O bus transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRANS_DEF: (counter: all)
number of completed defer transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_BURST: (counter: all)
number of completed burst transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_MEM: (counter: all)
number of completed memory transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents
BUS_TRAN_ANY: (counter: all)
number of any completed bus transactions (min count: 500)
Unit masks (default 0x40)
----------
0xc0: core: all cores
0x40: core: this core
0x00: bus: this agent
0x20: bus: include all agents


Thx
yyan

[Thomas_W_Intel]

Yyan,

2*(BUS_TRANS_ANY.ALL_AGENTS)/(bus frequency) gives you the address bus utilization.

e.g. if you see 123,456,789 events in 1 second and have a FSB freuency of 333MHz, this would imply 2*123,456,789 / 333,000,000 = 74% address bus utilization.

Kind regards

Thomas