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Issues Calculating Metrices related to L1I Cache, L2 Cache Metrices and Memory Bandwidth

Ysk966
Novice
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I started using V Tune as I need to collect few of the micro architectural metrics. I profiled using urach-exploration and memory-accesss.

Here is a summary of what I need and what I am having trouble getting. 

 

Metric Present in Current Set? Required Counters

IPC YesINST_RETIRED.ANY, CPU_CLK_UNHALTED.THREAD
CPI YesSame as IPC
L1D Hit / Miss / Access YesMEM_LOAD_RETIRED.L1_HIT, MEM_LOAD_RETIRED.L1_MISS
L2 Hit (Only Count) YesMEM_LOAD_RETIRED.L2_HIT
L3 Hit / Miss / Access YesMEM_LOAD_RETIRED.L3_HIT, MEM_LOAD_RETIRED.L3_MISS
Memory Stall Cycles (L1D, L2, L3) YesMEMORY_ACTIVITY.STALLS_L1D_MISS, STALLS_L2_MISS, STALLS_L3_MISS
DRAM Hits (Load) YesMEM_LOAD_UOPS_RETIRED.DRAM_HIT
Load / Store Instruction Count YesMEM_INST_RETIRED.ALL_LOADS, ALL_STORES
DTLB Walk Stats  YesDTLB_LOAD_MISSES.*, DTLB_STORE_MISSES.*

 

I still missing some counters and I really need that for research. Following is the table of what I require and not able to find

Metric Reason

L2 Miss / AccessStill no L2_MISS, L2_ACCESS, or inferred coverage
L1I Hit / Miss / StallNo ICACHE.* counters
L2 Hit CompositionNo breakdown counters or figure percentages
  

 

Have I missed looking at the specifications and documentations to get these missing metrices. For ICache Metrices, I was only able to found ICACHE_DATA.STALLS, ICACHE_TAG.STALLS which isnt a direct measure of getting the required stats. 

I really would appreciate in getting the help on getting these following metrices

@yuzhang3_intel 

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Ysk966
Novice
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@ThasneemV_Intel If you could help to provide how do I find L1 Instruction Cache Misses/Hits

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