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The cache latencies are listed in the Intel 64 and IA32 Architectures Optimization Reference Sect. 2.1.5 for Core architecture: L1 3 cycles L2 14-15 cycles Sect. 2.2.4 for Nehalem architecture: L1 4 cycles L2 ~10 cycles L3 35-40+ cycles Please read the respective sections for a more precise description.
