Question about L2 miss counting

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Question about L2 miss counting

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Hi,
here is a question regarding event counting on Xeon (Netburst) processors:
are software prefetches, performed with prefetch{t0,t1,nta} machine instructions, that miss in L2 taken into account for the calculation of the total number of L2 misses? I am using the 'BSQ_cache_reference' native event.

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