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icoming
Beginner
88 Views

count cache misses on Atom processors

Hello,
I'm trying to count cache misses on Atom processors. Ideally, I would like to count cache miss in L1. But after I searched the manualhttp://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/win/ug_docs/index.htm, I couldn't find any events that exactly count cache misses.
The closest one I found is MEM_LOAD_RETIRED.L2_MISS, which counts the number of cache misses caused by the load instruction.MEM_LOAD_RETIRED.L2_HIT also implies the number of cache misses in L1. However, it only counts cache misses caused by the load instruction. For example, if my program runs memset or memcpy, which doesn't use the load instruction but loads data to the cache, the two events don't work.
Now the question is how to count all cache misses on Atom processors no matter what causes them.
Thanks,
Da
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3 Replies
Kirill_R_Intel
Employee
88 Views

Try to use L2_LINES_IN like suggested in the following thread for Core 2:
icoming
Beginner
88 Views

OK. If I understand correctly, L2 misses should be L2_LINES_IN.SELF.DEMAND. I'm not convinced we should useMEM_LOAD_RETIRED.L2_LINE_MISS.
Peter_W_Intel
Employee
88 Views

L2_LINES_INis for L2 misses from both "Instruction prefetch" and "memory load".
MEM_LOAD_RETIRED.L2_LINE_MISS is for L2 misses from "memory load" ONLY.

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