Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
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AFU design with On-chip memory, How to debug on-chip memory of AFU design using system console


Hi all,


Remote debugging is necessary when you cannot access the JTAG connections.  So the application running on Intel PAC card is debug using remote debugging with system console over TCP/IP.  Use of signal tap we are able to debug our design, it's working fine.  To debug the on-chip memory using the system console, the design should have Avalon JTAG master IP instance, then we can use the system console master service to debug when FPGA connected using JATAG or USB blaster cable.  Here we debugging the design using the system console over TCP/IP, to access the system console master service, which masters service we need to access JTAG master service, processor master service, or TCP master.

we are accessing Avalon JTAG master service, we got an error message this master service is already claimed.  When I am accessing the TCP master service, so I claim the master service. But unable to read and write data to On-chip memory.

I have a question, is it necessary to have an ethernet IP/MAC  IP instance in our design, So it will help for accessing/connecting on-chip memory, like Avalon master IP instance for JTAG or USB cable.  Or we can use  Avalon master IP instance to access on-chip memory over TCP/IP using system console.

Please help me

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Are you referring to Chapter 6 AFU In-System Debug? If yes, then this AFU is using the Ethernet in order to performed the remote debug features capabilities.

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