Community
cancel
Showing results for 
Search instead for 
Did you mean: 
jAqui8
Beginner
240 Views

Altera PLL (cycloneV) getting locked to the wrong frequency.

I have generated a PLL with dynamic reconfiguration enabled.

Ref frequency = 160 MHz,

Target Frequency = 16 MHz.

before lock

reconfig_to_pll[63:0] = 0_3c000000

reconfig_to_pll[63:0] = 0_3c000001

after lock

reconfig_to_pll[63:0] = 0_10000003

reconfig_to_pll[63:0] = 0_10000002

 

It changes every half cycle of ref clk.

But after reset PLL is getting locked to 105.77 MHz. Though I am expecting it to get locked to 16 MHz. Is this behavior expected?

 

For experiment : I generated a PLL for 50 MHz ref clk . Target frequency 16 MHz. It is getting locked to correct frequency.

 

Attaching snapshot of the PLL behavior for 160 MHz ref_clk.

 

PS: Altera-pll ip core user guide doesn't give information about reconfig_to_pll signal. Please direct me to correct document.

0 Kudos
3 Replies
Rahul_S_Intel1
Employee
40 Views

Hi ,

Can you please try to follow the below PLL reconfiguration document.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an661.pdf

jAqui8
Beginner
40 Views

Hi Rsree,

 

Thanks for the reply!

 

I have followed that document.

I think the problem is with PLL IP. I tried generating PLL for reference frequency- 50 , 100, 105, 110, 160 MHz.

for fref 50 MHz : f tareget = 16 MHz --- PLL locked to ~16 MHz

for fref 100 MHz : f tareget = 16 MHz --- PLL locked to ~16 MHz

for above 100 MHz, ---pll is locking to some random frequency after reset.

 

PS: in all the above cases, the dynamic reconfiguration was enabled and connection between pll ip and reconfiguration block was made as per an661 document.

 

Regards,

Jawed

Rahul_S_Intel1
Employee
40 Views

Hi ,

The above behavior is wired, I have you check the below . Or any glitch in the input

 

Are the RREF pins connected correctly with its own individual resistor to GND

Are VREF and termination of the I/O standards set correctly? 

Reply