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DCP1.1 Clock Connections

JSchmidt
Beginner
1,036 Views

Dear all,

Moving from DCP1.0 to DCP1.1 I realized that there is a difference for the clock signals coming into green_bs.sv with regards to their sources.

The two I refer to are named Clk200 and Clk100 which are both generated by the same PLL inside the blue bits. In DCP 1.0, connections were as follows:

clock name / sourced by pin:

Clk200 / Pll_output [1]

Clk100 / Pll_output [3]

 

In DCP1.1 this has changed to:

Clk200 / Pll_output [3]

Clk100 / Pll_output [2]

 

The constraint files on the other hand do not reflect any potential change in frequency. According to this observation, in DCP1.1 Clk200 is actually a Clk100, and the Clk100 port is a Clk50.

 

I hope I didn't get anything wrong. Always happy to provide more explanations.

 

Thanks in advance,

Juri

 

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1 Reply
JSchmidt
Beginner
291 Views

Confirmed by Intel engineers: There is a clocking bug in DCP1.1 that leads to the observations mentioned in the opening post.

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