I am Yoji Yamato in Japan.
I used Dell PowerEdge R740 with Intel FPGA PAC D5005 (Intel FPGA Stratix).
This is a similar but other question from this one.
I would like to verify dynamic reconfiguration of FPGA using OpenCL.
When I execute dynamic reconfiguration of FPGA from mandelbrot OpenCL logics to sobel filter OpenCL logics, what should I do using Intel Acceleration Stack?
These are OpenCL files which are installed with Intel Acceleration Stack.
Dynamic reconfiguration means to update logics of FPGA during operation.
For example, while the Dell server computates mandelbrot using FPGA, the FPGA logics are updated to sobel filter by Remote System Upgrade or other means. I would like to know the means.
I would like to add some information.
Objective: Change FPGA configurtion based on user request trends at that time. To reduce service down time, dynamic reconfiguration is suitable than static reconfiguration.
Verification target: Dynamic reconfiguration of FPGA (not partial reconfiguration of FPGA).
Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.
My guess perhaps is to starting looking into how we can compile openCL kernels on PAC D5005.
Suggest to look into the guide here to setup/initialize the opencl with acceleration stack.
Please let us know if we misunderstand the situation.
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