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Novice
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How much private and local memory are available in Intel FPGA (pac_a10)?

For the OpenCL development on Intel pac_a10 (arria 10) FPGA, what's the maximum available size of private memory and local memory respectively?

 

Thanks

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Valued Contributor II
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There is no hardware separation of private memory and local memory on FPGAs. Depending on the size and memory access pattern of the buffer, the compiler might decide to use registers or Block RAMs to implement either storage type. The pac_a10 board employs an Arria 10 GX 1150 FPGA which has 1,708,800 registers (~1.5 MB) and 54,260 Kb of Block RAM (~6.6 MB).

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Novice
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I see. Thank you!

 

Could I clearly define a variable as a register one or Block RAM?

 

And does a register variable have a memory address? If so, a pointer to it can be passed to some function as the argument. In a traditional CPU architecture, a register variable has no "memory address".

 

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Valued Contributor II
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The decision of what resource to use for implementing buffers is directly made by the compiler. You can use the "__attribute__((register))" attribute in your buffer declaration to force buffers up to a certain size to be implemented using registers instead of Block RAM. However, there is a limit above which the compiler will refuse to perform this conversion and compilation will fail. It is usually best to leave the decision to the compiler.

 

There is no pointer for on-chip resources (be it register or Block RAM) and size of on-chip buffers must be known at compile-time. However, all on-chip buffers are addressable regardless of whether they are implemented using registers or Block RAM.

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Novice
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I defined a register variable and passed a pointer (to it) to a test function "foo" called inside the kernel ("int __attribute__((register)) a[10]; int *p = &a[1]; foo(p); "). The aocl can compile it successfully. So I guess you meant something else when saying "There is no pointer for on-chip resources" ?

 

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Novice
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Changed.

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Valued Contributor II
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All functions in the OpenCL kernel are inlined. This means that any pointer you use for on-chip resources will be evaluated and converted to direct addressing at compile-time. There is no run-time pointer chasing mechanism available on FPGAs. What I was trying to say was that pointers will not be implemented in the same way they would would be implemented on a CPU, rather than not work at all. If you use such a pointer in a way that the compiler cannot resolve the addressing at compile-time, it will fail to compile.

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Novice
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I see. Thank you for your clarification!

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