Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, DLA, Software Stack, and Reference Designs
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How to parameterize the single on-chip memory with different slave interfaces



I am designing the SoC using Quartus pro 19.2 of the platform designer tool. In this design, four different IPs are used to build the complete SoC.  Three master module IPs and one slave module IP, here slave IP is On-Chip Memory(RAM or ROM) Intel FPGA IP.  So three master modules communicate with single slave On-Chip memory, it has a memory bottleneck, each clock cycle only one request will be processed. To hence the throughput of memory, to instantiated another  On-Chip Memory(RAM or ROM) Intel FPGA IP, in this situation two slave interface and three master interface,  each clock cycle two request will be processed. The  On-Chip Memory(RAM or ROM) Intel FPGA IP has the option to parameterize memory type(RAM or ROM) and size(16, 32, 64, 128-bits). I want to know that, instead of instantiating the two memory block IPs to create two slave interfaces,  can I use single Memory IP to parameterize the slave interface (based on memory depth, for example, 0-1023 depth will access one slave interface and 1024 to 511 depth will access another slave interface in Single Memory IP instead two memory IPs instantiating ). Any way depth and width are parameterized in memory IP, is it possible to parameterize slave interface for single memory IP. I looked into the IP edit parameters tab, I didn't find any option to parameterize the slave interface. Please let me know if you have any input.


Thank you in advance for your time and consideration.



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3 Replies

You can parameterize your on-chip RAM to be a dual-port RAM.

There are two slave interfaces in dual-port RAM that can be read and write independently.

You can refer to below document.


On-chip RAM IP support the dual port RAM enable option, so we can have two slave interface, but in my design I am looking for more than two slave interfaces, Is it possible to parameterize On-chip RAM IP with more than two slave interfaces. 


Unfortunately you can't have an on-chip RAM with more than two slave interfaces.