How to write to and read data from an on-chip fifo through PCIE from a computer?

[SAbde7]

I am trying to write to and read from on-chip FIFOs from a C program running on a PC connected to an FPGA(Stratix V). I have been reading non-stop on the internet for the past week and I've come across a lot of different key concepts but can't get a big picture together that would allow me to have the understanding to implement the data transfer on my own.

I did however find an example program on the user-guide disk that inplemented the PCIE interface as well as writing to on-chip memory and DDR3 memory, and included a C library that I could use on the PC side that contained 

PCIE_Read32(), PCIE_DmaRead() and their write counterparts.

Since I still don't fully understand how the whole PCIE/DMA/AVALON system works, I would really appreciate input on how to connect a FIFO to this system on the Platform designer.

I tried connecting the read master of the PCIE to the out of the fifo, and the write master of the PCIE(v-series mm dma for pci express) to the in of the fifo but I got the following errors:

"Error:[...] pcie_256_dma.dma_wr_master is read-only while pcie_256_dma.dma_wr_master is write-only. "

(which makes absolutely no sense)

and

"Error: [...]: fifo_0.out is read-only while pcie_256_dma.dma_rd_master is write-only."

Connecting them the other way around was accepted(I left the 

in_csr and in_irq pins dangling because I don'know what to do with them) but that didn't work.

I will be adding a screenshot of the platform designer as soon as I can .

Here is the syntax I tried to used to access the FIFO from the PC:

#include "stdafx.h"

#include <stdio.h>

#include <stdlib.h>

#include <memory.h>

#include "PCIE.h"

#define DEMO_PCIE_USER_BAR PCIE_BAR4

#define FIFO_WRITE_MEM_ADDR 0x80020

#define FIFO_READ_MEM_ADDR 0x80024

...

BOOL bPass;

int* push;

bPass = PCIE_Read32(hPCIe, DEMO_PCIE_USER_BAR, FIFO_READ_MEM_ADDR,(DWORD)push);

and same for write.

what happens is that the "FIFO" behaves like a 32 bit register. I can only read the last value that I wrote, so if I write three times and then read, I will read the last write. If I keep reading I keep getting that last write, until I write again.

[Kenny_Tan]

Hi, Have you check out the design example shown in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an456.pdf page 12? Let me know if you have try it.

[SAbde7]

This is not relevant to my question. This is using the stratix hard ip for pci express. The reference design my question is about uses the v-series mm dma for pci express and therefore has completely different connections. I already have a PCIE system, I just want to connect a FIFO to it, not start over with another reference design that also has no explicit mention of FIFOs. Here is the screenshot of my system:

[Kenny_Tan]

You would like to connect the fifo to the PCIE for understand how the whole PCIE/DMA/AVALON system works? Unlike on chip ram, there are no address associated with it. Your software application will have to use address that matches the BAR to access the FIFO. Can you look into the https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/qts_qii55007.pdf page 16-7 on how to initialize and control the fifo?

[Kenny_Tan]

Is there update?

[SAbde7]

I have managed to communicate with the fifo using PCIE_Write32/Read32() and was experimenting with Dma_Write(), which worked, and Dma_Read(), which didn't work.

I don't need further assistance with connecting the FIFO in the platform designer. It seems the configuration I posted in the screenshot does work. I will be posting an answer to my own question soon for others who might face the same confusions as I did.