Application Acceleration With FPGAs
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I am working with Acceleration Stack Version 1.1 . How to change the frequency(uClk_usr uClk_usrDiv2) on the board? Does the uClk_userDiv2 have to be at half of uClk_user? I want uClk_usr to be 300M,and uClk_usrDiv2 to be 150M. what can i do ?

HYl
Novice
268 Views

ug-afu-dev-v1-1.pngTimeQuest_timing_analyzer.pngsignaltap.pngflow_message.pngchange_sdc.pngchange_json.png

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2 Replies
EBERLAZARE_I_Intel
187 Views

Hi,

 

Please read the 5.3.2.1.7. Specify AFU User Clock Timing

Section in our Accelerator Functional Unit Developer’s Guide for Intel FPGA Programmable Acceleration Card:

https://www.intel.com/content/www/us/en/programmable/documentation/bfr1522087299048.html

 

Let me know if there is further questions.

HYl
Novice
187 Views

Hi,

 I am working with DCP 1.1, not 1.2 or 2.0.1

 So this guide is not suitable for me.

 Please read the pictures in my attachment.

DCP_1.1.png

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