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HI,
I am using Msgdma memory mapped to Stream (in AGILEX -f agfb014r24b2e2v )(MM2S) with extended descriptor when i write the Descriptor and trigger the Dma data is streaming from the address of MSB (0x0 offset )
for example :
I am write some dummy data in address 0x1160000000
in 0x0 offset writing 0x60000000
in 0x14 offset writing 0x11
and triggering the dma but when i check in sys tap analyser data is streaming which is present in
0x60000000 only and ignoring msb
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Hi,
can you share your platform design?
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thank you for our reply
I am attaching the project file used 21.3 version
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hi,
i am using qsys_top.qsys
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Hi,
if you see here you didn't used SSBIN line. connect that line
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hi,
i am not using that ip. you can delete it
i checked connecting it but it is not working
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Hi,
Can you please enable bellow shown option?
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hi,
i tried with that setting but it is not working
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Hi,
https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335?wapkw=msgdma
please try this example project of MSGDMA.
in attached folder you can find out all drivers(software folder) and platform design.
Thank you,
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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