I am currently working on an application requiring a clock around 450 MHz. In order to do this, working on a Max10, I'm trying to generate the clock with the right frequency from the PLL.
Using the ALTPLL wizard, Quartus creates the dedicated component for me.
At the beguining, everything was going well, whether I start from an input clock of 50Mhz or 100Mhz, I always managed to make the PLL work correctly, to obtain output frequencies of 200 or 300 Mhz without problem. But then, past a certain frequency located around 320MHz, nothing was coming out from my PLL anymore, despite the "lock" bit telling me that the operation was successful.
At first I thought that the wizard did not correctly generate the coefficients (N: divider, M: multiplier, K: VCO post-scale), to be able to stick with the physical limits of my FPGA (VCO between 600 MHz and 1300 MHz / PFD entry between 5 MHz and 325 Mhz).
After having myself adjusted these coefficients throught the "Advanced PLL" file to fit with these limits, I come at the same result: nothing comes out of my PLL despite the bit lock up.
In addition, I cannot find how to manage the post-scalers of the counter (C0, C1, ..., C5). Only the VCO post-scaler K seems to be configurable.
Sorry for theses beguinners questions, but it blocks my work for weeks now.
Have a nice day !
I believe you are using Max 10 FPGA , I am kindly requesting to check the data sheet specification of PLL , page no: 26 of the below document for your reference.