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Register without clk signal.

HaiDs
Beginner
387 Views

 

Hello,

I am trying to create a register as shown in the picture so that there will be only memory storage.

I want it to have only a enable line that will only be enabled when I press the key.

The problem is that when I put it in the sensitivity lines of the process the compiler gives me a warning claiming that the key is not a clock line.this is actually what happend.this is actually what happend.this is the goalthis is the goal 

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3 Replies
SyafieqS
Moderator
329 Views

Hi Hai,


May I know if there is any update on this?


HaiDs
Beginner
324 Views

So basically I don't know how to create a Flip Flop. D latch. I thought of using the WHEN statement. but I don't see the FF in RTL viewer,

SyafieqS
Moderator
293 Views

Hi Hai,


You can refer to template to create Flip flop and register in insert template->verilog hdl->altera primitive-> fliflop/register. This a synthesizable code for Quartus which would help you to easier create FF with template.



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