I am trying to create a register as shown in the picture so that there will be only memory storage.
I want it to have only a enable line that will only be enabled when I press the key.
The problem is that when I put it in the sensitivity lines of the process the compiler gives me a warning claiming that the key is not a clock line.
You can refer to template to create Flip flop and register in insert template->verilog hdl->altera primitive-> fliflop/register. This a synthesizable code for Quartus which would help you to easier create FF with template.