I've designed a code in OpenCL, targeting Arria 10 FPGAs. In my design, I have specified parameters that control the size of the mode, with respect to the level of parallelism. As I grow this parameter, the model resource utilization grows as well, but stays below 80% of the maximum resources available (Based on the compilation report).
With specific high values, the compilation (better say fitting phase) seems to be never ending. It doesn't fail, but it stucks for more than a day. Based on my understanding, bigger designs leads into much higher complexity.
Now the question is, should I wait for the compilation, but there is no hope for the successful compilation? Does this mean that we can never fully utilize the available resources?
The estimation of the compilation report is not very reliable. Any compilation on Arria 10 that does not finish within 24 hours will likely never finish. You should be able to use all the DSPs and ~90% of the Block RAMs on Arria 10 without any fitting/routing failures. However, the story would be quite different with respect to logic; anything beyond 80% logic utilization will likely fail to fit or route.
A follow up question. Based on what you said, should I conclude that my design is consuming much larger resources compared to what is being reported? Or we are suffering from something like fan-out problem.
The correct switch is "-bsp-flow=flat". However, this switch is only applicable to v17.0+ and you have to manually check the timing report to make sure no signals have failed the timing. Note that using flat compilation disables PCI-E-based reconfiguration and requires configuration through JTAG and depending on your board and environment, you might have to reboot your machine for the kernel to work after that.