Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
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What happens to global memory bandwidth when Multiple OpenCL kernels read and write to DRAM simultaneously?




I have a basic question about how opencl compiler handles global memory access across different opencl kernels.


For eg:-

__kernel input1( __global int *r1 ) {




__kernel input2(__global char*r2) {




__kernel output(__global short *r3) {




When I launch the above three kernels parallely, does the memory bandwidth gets shared equally or does it depend on how many memory access? Does it depend on the size of the data type?


In general, what is the maximum number of read and write ports froim FPGA to Global memory?


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