programming DE5-net with custom BSP

[anaza3]

I am trying to program a DE5-net board with a custom BSP. the BSP is same as the one provided by trasic except that I added a module in the qsys file to read from DRAM some data and write it back to the DRAM(nothing really has to do with opencl module as it collects some other info about DRAM data). The module is tested with DRAM and works fine.

I changed the qsys file and set the variable ACL_QSH_COMPILE_CMD for base flow.

export ACL_QSH_COMPILE_CMD='quartus_sh --flow compile top -c base'

 I commented out these line in post-script

# Generate fpga.bin used for reprogramming
post_message "Generating fpga.bin"
if {[catch { call_script_as_function scripts/create_fpga_bin.tcl $revision_name.sof $revision_name.core.rbf $revision_name.periph_hash $revision_name } res]} {
  post_message -type error "Error in create_fpga_bin.tcl! $res"
 exit 2
}

and also deleted the persona directory. (I concluded I need to go through these steps based on this document(https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug_aocl_s5_net_platform.pdf)

I compiled the output by

aoc  device/vector_add.cl -board=de5net_a7 -report -v -o bin/vector_add.aocx

the compilation generates the project and compiles it and it all finishes successfully. I can see my module is added to the output when I look into the chip planner. However, when I try to program the board:

/trojan/tests/vector_add$ aocl program acl0 bin/vector_add.aocx
--------------------------------------------------------------------
No programming routine supplied.                                    
Please consult your board manufacturer's documentation or support   
team for information on how to load a new image on to the FPGA.     
--------------------------------------------------------------------

and when I try to flash with the aocx file:

aocl flash acl0 bin/vector_add.aocx 
aocl flash: Running flash from /tools/intelFPGA/18.0/hld/board/trasic/de5net/linux64/libexec
Failed to open file: 
aocl flash: Flashing failed. Error reading aocx file.

any idea that what step I am missing and what is causing this? why my aocx is not valid while the quartus project looks fine and compiled successfully? Is there any other way that I can program my fpga with the generated project?

[AnilErinch_A_Intel]

Hi ,

You have to check the content of the TCL script , create_fpga_bin.tcl

which you have commented out to understand about the root cause of the issue. How the script works is important in this case.

Thanks and Regards

Anil