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zjinf
New Contributor I
397 Views

shift register cause computational results error????

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Hi inteler/alteraer

i refer p130~131 on https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl-best-pra... write my code.

i found shift register will cause computational results error (1.0e-3f), that is integer parts and the first 2 bit of decimal also ok, no problem, but from the 3 bit , it will difference from PC ' results(for example : pc' results : 100.11234[FPGA without shift register also 100.11234], and fpga with shift register is 100.11341)

if i don't use shift register, the fpga's results is OK!

how can i fix the computational error!

 

thanks for your help!

 

 

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zjinf
New Contributor I
91 Views

hi HRZ

Thanks for your explanation ! it seems like what you say above

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HRZ
Valued Contributor II
91 Views

There is no "computational error" to fix. You are changing the order of the floating-point computations using that optimization, which will result in minor differences in the output due to rounding differences. Floating-point computations are not associative. If your application does not allow re-ordering of floating-point operations, you should not use that optimization. If you are using Arria 10/Stratix 10, that optimization is not required for single-precision floating-point reduction and you can use single-cycle accumulation instead. Check Intel's guides for more info.

zjinf
New Contributor I
92 Views

hi HRZ

Thanks for your explanation ! it seems like what you say above

View solution in original post

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