By Lori Scott, Senior Director of Marketing, Intel Foundry
In every region of the world, there are companies ready to benefit from the full-stack solutions enabled by a systems foundry and its trusted ecosystem partners. At the recent Intel Foundry Direct Connect Asia event held in Seoul, South Korea, numerous Asia-Pacific customers and partners interacted with Intel leaders in an intimate setting to discuss how our systems foundry offerings can help them accelerate and innovate. While the event enabled us to elaborate on key technology and partnership updates from our US event, the highlight of the show was the opportunity to listen to what our customers need to turn their ideas into AI-era solutions.
Ready with Silicon Commitments
In his keynote, Kevin O’Buckley, senior vice president and GM of Foundry Services, shared that Intel 18A is now in risk production and expected to reach volume manufacturing this year. Intel Foundry’s ecosystem partners have electronic design automation (EDA) enablement, reference flows, and intellectual property (IP) ready for production designs today.
He also touched on the following process technology updates:
- Intel 18A-P: Design rule compatible with Intel 18A, IP and EDA partners have already started updating their offerings for the Intel 18A-P variant to offer broader market coverage.
- Intel 18A-PT: New to the roadmap, the Intel 18A-PT variant is the first base die with backside power delivery, adding through-silicon vias (TSVs) to 18A-P for easy porting of IP.
- Intel 14A: Featuring PowerDirect, a new direct contact power delivery, the Intel 14A Process Design Kit (PDK) has been delivered to lead customers while multiple test chips on the new node are in process.
- Intel 16, Intel UMC 12, and Intel 3: Intel Foundry’s first production 16 nanometer (nm) tape-out is in the fab now. The commitment to our roadmap, development, and evolution of mature nodes, including Intel 3 and 12nm in collaboration with UMC, remains unchanged.
O’Buckley also recapped the following updates related to advanced packaging:
- EMIB-T: Adding TSVs to the Embedded Multi-die Interconnect Bridge (EMIB-T) enables future high bandwidth memory needs for AI and data center applications.
- Foveros 2.5D portfolio expansion: The addition of redistribution layers in Foveros-R and bridges in Foveros-B to our existing silicon interposers in Foveros-S provide efficient and flexible chiplet stacking options for customers.
- Improving supply chain resiliency: Intel Foundry is expanding advanced packaging capacity with outsourced semiconductor assembly and test (OSAT) locations opening in Korea in 2026.
In addition, O’Buckley highlighted two new programs added to the Intel Foundry Accelerator alliance of ecosystem partners:
- Chiplet Alliance: Provides a scalable path for deploying designs using interoperable and secure plug-and-play chiplet solutions for targeted applications and markets.
- Value Chain Alliance (VCA): This network of system companies can design and deliver application-specific integrated circuit (ASIC) and system on chip (SoC) solutions.
See the full US Direct Connect keynote video for all updates.
Process Technology Innovations Deep Dive
In addition to outlining power, performance, and area (PPA) optimizations provided by Intel 18A, Intel 18A-PT, and Intel 14A, Myung-Hee Na, Intel Foundry vice president and GM of technology systems, highlighted Turbo Cells in her presentation on process technology innovations. This boosted cell technology further enhances maximum CPU frequency and amplifies performance for critical paths in GPUs when paired with RibbonFET 2, our second-generation gate-all-around technology (GAA). Turbo Cells allow designers to optimize a mix of more performant cells and more power-efficient cells within a design block, enabling a custom balance between PPA for target applications.
She also focused on the challenge of increasing resistance-capacitance (RC) delay in interconnect materials as transistors continue to shrink in size. Intel Foundry’s forward-looking silicon innovations include extreme transistor and interconnect scaling techniques for delivering energy-efficient and high-performing solutions for compute-intensive applications such as HPC and AI. Our silicon RibbonFET gate-all-around transistor technology offers ultra-short gate length scaling at 6nm for area- and power-sensitive applications.
Using system technology co-optimization (STCO), we’re optimizing chiplet-based designs by understanding the interplay of various components within a single package. To enable higher throughput for ultra-fast chip-to-chip assembly in advanced packaging for AI applications, we’re using selective layer transfer (SLT). This heterogeneous integration solution enables ultra-thin chiplets with much better flexibility, allowing smaller die sizes and higher aspect ratios versus traditional chip-to-wafer bonding.
Watch the US Direct Connect process technology innovations video for more information.
Updates on Integrating with Advanced Solutions
We were honored to celebrate the illustrious career Dr. Choon Lee, Intel Foundry vice president and GM of packaging and test, as he gave an update on integrating with advanced solutions. Lee talked about Intel Foundry’s integrated capabilities across advanced system assembly and test, encouraging the audience to consider Intel Foundry as one of their OSATs.
He also shared an in-depth review of new advanced packaging roadmap additions, offering details on:
- EMIB-T: Enables high-bandwidth, low-latency communication between chiplets within a single package. With the key addition of TSVs and high-power metal-insulator-metal (MIM) capacitors, EMIB-T offers vertical power delivery for die-to-HBM4 stitching to minimize DC and AC noise when connecting a logic die to high-bandwidth memory.
- Foveros: Foveros-B 2.5D, Foveros-R 2.5D, and Foveros Direct 3D offer variable bonding methods, successively denser pitches, and support for use cases from high-density AI through edge, wearables, and low-power devices.
- Co-packaged optics: Intel is advancing its co-packaged optics technology to enable higher bandwidth, power efficiency, and density in data center and AI systems.
- Socket technology: Intel also has a robust socket technology roadmap to support high-speed interfaces like PCIe 7.0 and DDR6 RAM with both LGA capability and compression mount sockets.
See the US Direct Connect advanced packaging technology update for further details.
Moving Forward in Building Relationships
Intel Foundry Direct Connect Asia provided our Intel Foundry team with valuable customer insights and the opportunity to build stronger relationships. We know our customers need trusted partners on this journey, and we’re energized and ready to deliver the performance, quality, and reliability they need to succeed. We’re looking forward to continuing these critical conversations throughout the year as we look ahead to our future Direct Connect events in 2026.
For more information on news shared at our Intel Foundry Direct Connect events, please see the full playlist of Direct Connect US presentations or reach out to foundry.contact@intel.com.