For nearly 60 years, Intel has delivered the future technologies that drive the entire semiconductor industry forward and define what is possible for the next generations of computing. Innovations such as Strained silicon, High-k/metal gates, FinFETs, RibbonFETs, and PowerVia have advanced Moore’s Law and propelled Intel and the whole industry to an era where we can build systems with billions of transistors in high-volume for the most challenging problems today - whether at the edge, in consumer devices, or the latest AI datacenters.
At IEDM 2024, Intel Foundry Technology Research published seven papers giving insight into our view of key challenges in advanced packaging, transistors, and interconnects over the coming decade and detailing some of the critical breakthroughs that are advancing the state-of-the-art. With these and other research contributions, Intel Foundry continues to pave the way for the future of semiconductor manufacturing and the delivery of trillion-transistor systems by 2030.
Advanced Packaging
Advanced packaging is an area of tremendous innovation across the industry. In an invited paper (Swan, et al., 2024), we discuss the growing demand for AI systems and capabilities and how these can be addressed through tighter memory integration, scaling hybrid bond pitch, and modularity for expansion. Modern AI applications such as large language models are limited by memory capacity, bandwidth, and latency, which have trailed compute capabilities by a factor of two or more. Hybrid bonding between memory (e.g., DRAM) and compute (e.g., logic), such as with Intel’s Foveros Direct 3D technology, can eliminate these bottlenecks. Scaling the hybrid bonding pitch from ~10um, which is common today, down to 0.4um will radically improve the energy efficiency and performance of future systems but requires assembly and packaging flows that embrace higher-precision approaches from silicon wafer fabrication. At the same time, the AI applications of today often span a rack or an entire data center and require expansion between multiple systems. Rethinking packaging to incorporate this system-level expansion in a modular fashion will vastly improve the industry’s economics and efficiency.
One of the crucial benefits of advanced packaging is the flexibility to assemble chiplets from different manufacturing technologies, such as DRAM and logic, together to form a single system that combines the best of different technologies. Presently, this is accomplished with either a fast and inflexible wafer-to-wafer bonding process or a slower, more expensive, and more flexible chip-to-wafer bonding process. A second paper from Intel Foundry (Elsherbini, et al., 2024) introduces an advanced packaging breakthrough that employs novel inorganic laser debonding for selective layer transfer between two wafers. This unlocks wafer-to-wafer hybrid bonding processes with the flexibility of chip-to-wafer bonding and 100X faster throughput – bending the cost curve and unlocking new opportunities for heterogeneous integration.
Advanced packaging in turn creates more openings for novel chiplets and materials, such as Gallium Nitride (GaN), to improve the capabilities, cost, and power efficiency of the overall system. Gallium Nitride (GaN) is a wide bandgap semiconductor that is ultra-efficient for power electronics and radio frequency communication but has been challenging to widely adopt. Over the last decade, Intel has pioneered integrating highly scaled GaN transistors on 300mm silicon wafers, paving the way to transform the economics and capabilities for power electronics. Building on this work, a third paper (Then, et al., 2024) demonstrates integrating a full suite comprising highly-scaled and high-voltage GaN transistors on a novel 300mm trap-rich silicon-on-insulator (TR-SOI) wafer. Using the novel TR-SOI boosts the substrate resistance by 4X, which significantly improves signal quality and efficiency for a wide range of radio frequency applications and power applications.
Transistors
Turning from packaging to transistors, the industry is on the cusp of the transition from FinFET devices to stacked RibbonFETs, led by the Intel 18A process node. Continuing Moore’s Law over the next decade will require scaling the dimensions of RibbonFETs to improve density. In a first transistor paper (Agrawal, et al., 2024), Intel Foundry’s researchers demonstrate the viability of reducing the gate length of a silicon RibbonFET below 10nm. Through careful engineering and characterizing RibbonFETs, Intel’s researchers established excellent transistor performance with gate length as small as 6nm, creating significant headroom for scaling RibbonFETs over the coming years.
One possibility for scaling transistors beyond RibbonFETs is replacing the silicon channel with transition metal dichalcogenides that operate as semiconductors with a single molecular layer (so called 2D materials), thereby enabling even smaller transistors. In a second transistor-focused paper (Mortelmans, et al., 2024), we demonstrate new performance records for both NMOS and PMOS gate-all-around transistors using 2D materials. Through careful engineering of a new gate oxide process at compact ~30nm gate lengths, Intel researchers achieved record-setting performance including a 2X improvement in NMOS drive current at 1V operation. These performance results improve the feasibility of 2D transistors, while also identifying future challenges to development.
Finally, in an invited talk (Ghani & Ranade, 2024), Intel Foundry researchers share an ambitious vision for the future of transistor scaling and the roadmap for reaching one trillion transistors and beyond. As the number of transistors increase, power consumption and energy efficiency become the ultimate limiting factor. While current transistors can operate at approximately 1V, new types of transistors are needed that can deliver good performance below 0.3V to radically improve energy efficiency. At these voltage levels, many traditional materials no longer provide compelling performance and new higher-mobility materials are needed to address the low voltage. Candidate technologies such as tunnel FETs, ferroelectric FETs, and negative capacitance FETs all show potential promise and merit exploration. Collaboration between industry and academia delivered the past 60 years of success and will be vital to defining future possibilities.
Interconnects
The success of the industry in transistor scaling also creates challenges for the metal interconnects between transistors. Future process nodes will require interconnect pitches below 20nm, where existing materials such as copper have degraded resistance, limited aspect ratios, and lack compatibility with low-k and air-gap dielectrics. Intel Foundry and the industry have identified subtractive ruthenium patterning as a promising replacement that addresses these three challenges. Our researchers demonstrated (Dutta, et al., 2024) the first R&D test vehicle using an economical and high-volume compatible subtractive ruthenium patterning process with air-gap dielectrics. The test vehicle illustrated healthy defect and electrical behavior across a full wafer and delivered up to 50% improvement in capacitance for 20nm pitch using subtractive ruthenium with air gaps compared to copper.
2025 and Beyond
The papers we shared at IEDM 2024 give a peek at the type of foundational science driven within Intel Foundry by organizations like Technology Research. While some may look at these developments as “science fiction,” they may soon be “science fact.” Key innovations we’re bringing to market in 2025, including PowerVia and RibbonFET as part of our Intel 18A process node, were detailed at previous conferences. With this in mind, we invite you to watch this space in the future, as we continue to update from the frontiers of semiconductor research.
Research Discussed in This Piece
Agrawal, et al., "Silicon RibbonFET CMOS at 6nm Gate Length," IEDM, 2024.
Dutta, et al. "Subtractive Ruthenium Interconnects with Airgap," IEDM, 2024.
Elsherbini, et al., "Selective Layer Transfer: Industry First Heterogeneous Integration Technology Enabling Ultra-Fast Assembly & Sub-1um Chiplet Thickness for Next Generation AI & Compute Applications," IEDM, 2024.
Ghani & Ranade, "The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead," IEDM, 2024.
Swan, et al., "Tomorrow’s Modular & Scalable Compute Systems," IEDM, 2024.
Mortelmans, et al., "Gate oxide module development for scaled GAA 2D FETs enabling SS<75mV/d and record Idmax>900µA/µm at Lg<50nm," IEDM, 2024
Then, et al., "30nm Channel-Length Enhancement-Mode GaN MOSHEMT Transistors on a 300mm GaN-on-TRSOI Engineered Substrate," IEDM, 2024.
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