Most industry watchers believe that hyperscale data center network traffic volumes will continue growing at a dramatic rate. Barefoot Networks was founded on the premise that programmability will be essential in these data centers to ensure network agility. With our Intel® Tofino™ switch ASICs, we delivered on that promise with a switch ASIC that delivers P4 programmability without a penalty on power.
When we joined Intel, we knew we would be able to work with the best in the industry to expand this vision for the future. I am very proud to highlight one of our first end-to-end collaborations across the Intel portfolio of products, which co-packages photonic engines with an Intel Tofino 2 switch.
Intel Silicon Photonic Engines and Intel Tofino 2
Growth in data center bandwidth is changing data center connectivity needs. In March, we announced a demonstration of the very first working co-packaged optics Ethernet switch, which combines the Intel Tofino 2 switch with photonic engines from Intel. Intel Tofino 2 continues to deliver full-pipeline programmability with P4, which is a big advantage in a modern hyperscale infrastructure.
Intel Tofino 2 Multi-Die Design
Intel Tofino 2 switch ASIC has a unique ability to support co-packaging of multiple different types of I/O (input/output) tiles, including optics, due to its tile-based design, which features a monolithic core die plus interface tiles that can be swapped out to support different speed electrical SerDes, as well as optical photonic engines.
To date, we’ve used this flexibility to offer different ASIC SKUs that use the same switch core but vary the number and data rate of the interface tiles to offer different power / price / performance profiles ranging from 4.0 Tbps up to 12.8 Tbps. In the co-packaged optics demo, we extended this capability to utilize 1.6 Tbps photonic engines realized as four ports of 400GBase-DR4 interfaces, based on the Intel silicon photonics platform.
Below is a picture of the platform we built. The heat sink has been removed from the switch ASIC so you can see the rest of the components. The copper colored thermal management system on the sides is used to manage the heat generated by the photonic engines. The metal wires in the foreground support today’s pluggable connectors showing the flexibility of the split-die design to support hybrid connectivity.
For those who want to better understand the silicon photonics elements of the design, read this blog post that goes into more detail on the silicon photonics innovations included in this demonstration platform.
The working platform is an important milestone because as switch ASIC capacity reaches 25Tbps and SerDes connections reach 112G, the industry will be forced to move to co-packaged optics. While these technology evolutions are still years in the future, Intel can now move forward developing the additional IP that will be needed to make a complete solution. With this demonstration, we believe we’re on-track to deliver commercial co-packaged optics/Ethernet solutions within two switch generations, in-line with predicted customer needs.
This co-packaged solution continues to showcase the value of using both Intel Tofino ASICs and Intel’s silicon photonics technology for next generation hyperscale data center solutions. For more information on Intel’s progress to deliver optical I/O co-packaged with networking silicon, please visit the Intel Newsroom and check out my colleague Hong Hou’s post on the topic. For more information on Intel’s Barefoot Networks division and Intel Tofino 2, please visit https://barefootnetworks.com.
Edward (Ed) V. Doe is vice president of the Connectivity Group and general manager of the Barefoot Division (BXD) at Intel Corporation. Doe holds a bachelor’s degree in electrical engineering from the University of Western Ontario, London, Ontario, Canada and two years of graduate studies towards a master’s degree in electrical engineering at Stanford University.