We are excited to announce the release of Quartus Prime Pro 25.1, which supports the newest Agilex family, Agilex 3. This update equips developers with advanced tools for building high-performance, power-efficient edge and embedded applications.
Comprehensive Support for Agilex 3 FPGAs
The Agilex 3 FPGA family brings high performance, power efficiency, and cost optimization to edge and embedded applications. With this release you can design, test, and deploy solutions more effectively utilizing the Agilex 3 higher-speed transceivers for improved connectivity, on-chip dual Cortex-A55 ARM cores, adding powerful processing capabilities, and expanded memory support, including LPDDR4.
For applications where board space is limited, Agilex 3 utilizes Intel’s variable pitch BGA packaging to enable more compact and efficient designs. This technology allows developers to fit more functionality into smaller footprints while maintaining performance and power efficiency.
Security is essential for protecting intellectual property and sensitive data in FPGA applications. Agilex 3 includes new features that strengthen encryption, authentication, and physical security, making designs more resilient to tampering and attacks.
Nios® V Soft Processor Enhancements
The Nios V plays a crucial role in embedded applications, and this release brings performance and efficiency improvements. These updates enable developers to build more compact, higher-performing embedded systems.
- Nios® V/g Core Performance Boost –Improved task execution efficiency and optimized overall performance
- Nios® V/c Core Area Reduction – Achieves an 8% area reduction, making designs more compact.
- Ashling RISCFree™ IDE VS Code Extension – Provides a Visual Studio Code extension for streamlined Nios® V software development using Ashling RiscFree IDE.
- TinyML Example Design using Nios V Application Note – Enables developers to integrate machine learning (ML) capabilities into FPGA designs using microcontrollers
Embedded Software Features
FPGA-based embedded applications require robust OS and virtualization support. Quartus Prime Pro 25.1 expands compatibility for Linux, RTOS, and hypervisors, allowing developers to create scalable, real-time, and virtualized embedded solutions.
- Linux Hardware Reference Designs – Standard and regular editions for seamless Linux development.
- Xen Hypervisor Support – Allows developers to build virtualized environments for FPGA applications.
- RTOS Support – Supports Zephyr and Bare Metal, with FreeRTOS coming in Q2 (May release).
Installer Improvements: Faster, More Flexible Setup
Installing FPGA software should be efficient and customizable. Quartus Prime Pro 25.1 improves the installation experience with parallel processing, flexible component selection, and better file management.
- Parallel Installation – Reduces setup time by allowing multiple components to install simultaneously.
- Dynamic Component Selection – Lets users choose only the components they need, optimizing disk space and installation time.
Streaming Debug: High-Speed Hardware Debugging
Effective debugging is key to reducing development cycles. The Streaming Debug IP for Signal Tap provides real-time, high-bandwidth data capture, improving how developers analyze and troubleshoot FPGA designs.
- High-Speed Streaming for Hardware Debugging – Enables efficient data transfer for real-time analysis.
- Configurable Streaming via STP – Use Signal Tap Logic Analyzer (STP) to configure the streaming method and select the appropriate debug host.
Simulation Improvements
Quartus Prime Pro 25.1 introduces new native Altera AXI4 Bus Functional Models (BFMs), delivering improved simulation performance, integration, and long-term support.
- Native Altera AXI4 BFMs – Optimized for Quartus simulation workflows, ensuring better compatibility and performance.
- Seamless Transition – Users can switch to the new Altera AXI4 BFMs without significant modifications, benefiting from tighter toolchain integration.
Quartus Prime Pro 25.1 brings significant simulation performance improvements, particularly for transceiver protocol IP, leading to faster and more efficient debugging and verification.
- Improved Transceiver Protocol IP Simulation – Enhances support for PCIe, Ethernet, Serial Lite, JESD, and other transceiver protocols.
- Beta Models in 25.1 – The new simulation models are in Beta for this release, with a focus on Ethernet and PCIe.
- Enhanced Performance – Improvements of up to 50% or more are typical, reducing simulation time and accelerating verification.
These simulation updates make Quartus Prime Pro 25.1 a more powerful tool for transceiver-based FPGA designs by delivering faster, more efficient simulations and reducing overall verification time.
Additional Updates in Quartus Prime Pro 25.1
Containerized Images for Quartus Prime Design Suite (QPDS) Standard & Pro –Containerized versions of Quartus Prime Standard and Pro Editions are available from Docker Hub, simplifying deployment and improving compatibility with cloud and CI/CD workflows.
Static Timing Analysis Improvements: Smarter Design Closure
- Design Closure Summary – Separates timing closure results from Design Assistant results, providing clearer categorization of different failure types.
- SDC Relative File Paths in Reports – Simplifies script management and improves portability for Synopsys Design Constraints (SDC) reports.
- MTBF (Mean Time Between Failure) Improvements – Gives users fine-grain control over the toggle rate of specific instances to address MTBF failures when default toggle rates are not ideal.
Quartus Prime Pro 25.1 enhancements to static timing analysis, making it easier to diagnose and resolve timing issues efficiently.
RAM Inference Improvements: Enhanced Synthesis Support
- Support for Simple Quad-Port RAM in Synthesis – Enables automatic inference of simple quad-port RAM, improving flexibility in memory architectures.
- Complete Support for Byte Enable Inference in Synthesis – Expands support beyond just 8-bit byte enables to now include 5, 8, 9, and 10-bit configurations, aligning with full hardware capabilities.
- More Precise Control – The byte enable control signal now allows users to write individual bytes within a word, optimizing memory access and performance.
Enhanced RAM inference capabilities make it easier for designers to take advantage of FPGA memory resources efficiently.
FPGA AI Suite: Expanded AI Capabilities and Enhanced Usability
As AI adoption continues to grow, FPGA-based inference solutions need to be more flexible and efficient. This release introduces improved model support, better performance estimation, and enhanced integration with Agilex FPGAs.
Key Enhancements
- Agilex 3 Beta Support – FPGA AI Suite now provides beta-level support for Agilex 3 FPGAs. User can generate Inference IP targeting Agilex 5 in architecture config file and compile in Quartus using Agilex 3.
- Altera Rebranding – RPM and DEB packages are now renamed to "altera-fpga-ai-suite-<version>", and AI Suite now installs into "/opt/altera" instead of "/opt/intel".
- YOLOv7 Model Support – Enables high-accuracy object detection in industrial quality control, surveillance and robotics applications.
Example Designs & Usability Improvements
- Agilex 5 FPGA E-Series Example Design Support – New example designs available for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit.
- SoC Example Design – Demonstrates AI inference with ARM as the host processor. New Layout Transform integrated with AI Inference IP – Supports folding and run-time configurability enabling optimization of AI models for improved performance & usability.
- Hostless JTAG-Attach Example Design – Hostless design with a system console connected to the Inference IP via JTAG, allowing users to configure and control IP functions through a guided step-by-step process.
Performance & Software Enhancements
- Performance Estimator Takes Memory Bandwidth – Unlike previous versions, users can now specify available external memory bandwidth, improving accuracy when designing for memory-limited devices like Agilex 5 and Agilex 3.
- OpenVINO 2024.6 Integration – FPGA AI Suite 25.1 moves to the latest OpenVINO 2024.6 release ensuring stability and maintainability.
- Long-Term Support – AI Suite will be limited to two years of Quartus Prime Pro releases, leveraging new optimizations, performance improvements.
With these updates, FPGA AI Suite 25.1 makes it easier to deploy AI inference on FPGAs, providing better performance, broader example designs, and new model support.
IP Features in Quartus Prime Pro 25.1
Quartus Prime Pro 25.1 introduces new IP cores for Agilex 3 and key updates for Agilex 5, enabling high-speed connectivity, flexible memory access, and real-time data processing capabilities for a wide range of applications.
Introducing Agilex 3 IPs
Agilex 3 now includes a robust set of connectivity, memory, and processing IPs designed for cost-optimized applications:
- Flexible I/O Support – High-voltage, high-speed interfaces including MIPI D-PHY and 1.25 Gbps LVDS.
- High-Speed Data Transfer – 12.5Gbps transceivers, PCIe 3.0, and 10GE Hard IP for reliable high-bandwidth applications.
- Cost-Effective Memory Support – LPDDR4 up to 2133Mbps for efficient embedded memory solutions.
- Seamless ARM Cortex Integration – HPS EMIF ensures tight integration with ARM processors.
- High-Resolution Video & Image Processing – VVP suite accelerates video and vision processing applications.
- JESD204B for Data Converter Synchronization – Enables precise multi-channel synchronization at 12.5Gbps.
- Advanced Debugging with Transceiver Toolkit – Improved transceiver link testing and debugging.
Agilex 5 IP Updates
The Agilex 5 family IP receives performance and flexibility enhancements, including:
- Dynamic Reconfiguration – Real-time adjustments of multiple configurations via PMA-Direct
- Multi-Channel DMA for PCIe 3.0/4.0 – Supports x2/x4 PCIe with both Root Port (RP) and Endpoint (EP) modes.
- Interlaken @ 12.5Gbps per Serial Lane – Introduced in Agilex 5 D Series, enabling scalable data transmission.
- JESD204B @ 17.16 Gbps with Advanced debugging using Transceiver toolkit – Ensures high-speed, high-precision data transfer.
- JESD204C Protocol in Dual-Simplex Mode – Expands high-speed ADC/DAC connectivity for advanced signal processing.
- O-RAN IP - Supports 15-240 KHz of sub carrier frequencies and real-time sub carrier spacing adjustments through control messages. Digital power scaling and saving features.
With these updates, Agilex 3 and Agilex 5 FPGAs offer greater performance, efficiency, and flexibility, making them ideal for embedded, networking, and AI-driven applications.
Conclusion
Quartus Prime Pro 25.1 delivers major improvements across Agilex 3 support, debugging tools, AI acceleration, IP cores, and overall usability. Whether you're optimizing for high-speed interfaces, AI workloads, or embedded applications, this release enhances performance, efficiency, and flexibility.
Visit the Quartus Prime Pro website to learn more.