Altera was excited to unveil a group of revolutionary solutions highlighting the value of FPGA-based AI for wireless communications. With a diverse array of demonstrations and showcases, Altera highlighted the performance per watt advantages of Agilex™ FPGAs and SoCs plus the ease of use of its AI and DSP software tools and IP for wireless applications.
Figure 1. mMIMO Enablement Package Radio Board using Agilex 7 FPGAs at MWC 2025
A Wall of Radios: Showcasing Versatility and Innovation
One of the highlights of our exhibit was Altera’s Wall of Radios, featuring eight models from our partners and customers—Syntronic, Tejas Networks, Massive Beams, Radisys, Intel, Comba, and BMI. Each radio was powered by Altera FPGAs, and many demonstrated the ease of deployment and fast time-to-market made possible by our Radio Enablement Packages. These solutions catered to a wide range of applications, from Small Cell and Macro to mMIMO, offering our customers unparalleled flexibility and performance in radio deployments.
Figure 2. Altera Wall of Radios at MWC 2025
AI Demos: Pioneering the Future of Radio Access Networks
In addition to our radio showcase, we were thrilled to present a series of AI demos that underscored our leadership in deploying AI solutions on FPGAs. Our engineers worked diligently to explore and implement innovative use cases for AI in the Radio Access Network (RAN), and we are eager to share these advancements with everyone. Please follow us as we periodically release detailed information for each demo video we feature over the next few months.
- Demo: AI-Based Timing Sync on Altera® SoC FPGAs | Synchronize the RAN during Holdover
Our AI-based approach for timing synchronization in RAN used MLP and LSTM models on Altera SoC FPGA to predict clock drift and maintain stability during holdover. This method fine-tuned the DPLL for accurate frequency, reducing both costs and power usage by up to 10x. Tests run over multiple days confirmed DPLL adjustments during holdover, enhancing RAN performance. This design example was based on Altera’s market-leading PTP/Servo IP, updated to support AI.
- Demo: AI-Driven Channel Estimation with Altera® SoC FPGAs | Boost 5G Throughput & Efficiency
This demo highlighted our AI-driven approach to channel estimation, leveraging Convolutional Neural Networks (CNNs) on Altera Agilex SoC FPGAs. Experiments showed a 20% higher throughput in low-SNR conditions, demonstrating improved performance and reliability for 5G and future 6G networks with AI. - Demo: Neural Network Channel Estimation on Altera® SoC FPGAs | Efficient AI for 5G Radio Units
Implemented using Altera AI software, this demo featured a Multi-Layer Perceptron (MLP)-based neural network that efficiently estimated channel coefficients. It achieved a throughput of 12K DMRS-based channel estimations per second for mMIMO systems, with substantial resource savings, highlighting the potential of AI-aided algorithms in enhancing 5G communication systems. - Demo: Achieve 1,000x Channel State Information (CSI) Compression with AI autoencoders on Altera® Agilex™ SoC FPGAs | Optimizing 5G Bandwidth
Channel State Information (CSI) was crucial for stable 5G connections, but frequent updates caused high signaling overhead. Our autoencoder-based compression method reduced this overhead by about 1000x while maintaining a near-perfect match (0.9999+ correlation) between original and reconstructed data. Implemented on Altera’s Agilex SoC FPGA using FPGA AI Suite and OpenVINO, this solution streamlined 5G traffic, met 5G Rel-17 standards, and paved the way for 3GPP Rel-18 toward 6G advancements. - Demo: AI-Enabled DSP Design on Altera® FPGAs | Optimize Cost & Performance
This demo explored the integration of AI models with traditional DSP processes using Altera’s DSP Builder Software. By providing a unified environment for experimentation and optimization, designers easily found the optimal cost/performance balance, resulting in commercially optimized implementations. This design example was also based on Altera’s PTP/Servo IP. - Demo: Deploy AI Models in Software and Hardware within Hours | Altera® FPGA AI Suite + Open FPGA Stack (OFS). By combining FPGA AI Suite with Open FPGA Stack (OFS), we enabled the seamless deployment of AI/ML models on Agilex FPGAs. This integration transformed high-level models into optimized hardware in hours, facilitating rapid evaluation and scaling of AI workloads. The process was streamlined and efficient, empowering developers to achieve FPGA-accelerated execution with minimal effort.
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