CAST and Fraunhofer IPMS offer a scalable Time Sensitive Networking (TSN) solution from Altera’s Low Power & Cost Optimized FPGAs to the latest Agilex™ 3 and Agilex™ 5 FPGAs
The Challenge: Bringing Precision Timing to Ethernet
Traditional Ethernet, while dependable for general networking, falls short in meeting the requirements of evolving automation technology. These applications often require real-time control, microsecond-level time synchronization, guaranteed bandwidth, and ultra-low latency scheduling. This has led to the development of various proprietary bus systems that use Ethernet on a physical level but implement their own real-time protocols, resulting in vendor dependencies and fragmented networks. These systems often separate time-critical data traffic from less-critical traffic to avoid interference, which isn’t suitable for future Industry 4.0 applications, automotive systems, or avionics, that demand more consistent and integrated Ethernet networks.
Time-Sensitive Networking (TSN) is a set of protocols built on well-established, standard Ethernet technology that is advancing to meet these needs. It provides a standardized solution that ensures reliable, deterministic, and low-latency communication over Ethernet. TSN enables the convergence of critical and non-critical data traffic on a single network, eliminating the need for separate infrastructures, and thus reducing costs. By guaranteeing latency times and eliminating vendor dependencies, TSN is essential for real-time communication.
Efficiently integrating these complex TSN mechanisms demands specialized hardware and software that go beyond typical network interfaces. CAST and Fraunhofer IPMS, experts in silicon IP and communication protocols, are leading this charge, offering solutions with unmatched flexibility and resource efficiency when implemented on Altera FPGAs.
The Solution: Compact TSN IP on Altera FPGAs
CAST and Fraunhofer provide TSN End Point, TSN Switch, and TSN Switched Endpoint IP cores that can be used to build a TSN Ethernet network, designed to overcome the limitations of standard Ethernet. Unlike less integrated approaches, this solution provides the essential building blocks for deterministic communication, embedding critical time synchronization and traffic scheduling features directly into the hardware. These cores are optimized for resource efficiency, minimizing logic demands within the FPGA for cost-effective designs, while offering flexibility to tailor TSN nodes for specific application needs
Altera FPGAs provide the flexibility and efficiency needed in most TSN applications. TSN is often the backbone of an industrial automation or in-vehicle network where the network nodes typically communicate with sensors or actuators through a variety of interfaces, including SPI, CAN, PWM, and more, and may need to run simpler or more complex software layers. By implementing TSN on Altera FPGAs, developers can implement different interfaces, device drivers, and software application layers on the same, cost-effective device.
Altera FPGAs, like the low-power and cost-effective Cyclone® V SoC FPGA, provide an ideal hardware foundation because of their flexibility, performance, and rich IP ecosystem. The TSN IP's digital and compact nature ensures easy portability to the latest Altera device families, like the high-performance and power-efficient Agilex™ 3 FPGA, or the mid-range Agilex™ 5 FPGA with infused AI blocks.
Proven TSN IP Cores
CAST offers three TSN cores ready for implementation on Altera devices:
- A multiport TSN Ethernet Switch supporting cut-through, ultra-low latency operation
- A TSN Ethernet Endpoint suitable for star network topologies
- A TSN Ethernet Switched Endpoint suitable for daisy-chained networks
Created by Fraunhofer IMPS to meet CAST’s rigorous IP quality standards, each TSN core provides an efficient, easy-to-integrate, and low-risk hardware implementation. The cores support the essential TSN timing synchronization and traffic-shaping protocols—i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br—and optionally support additional TSN protocols for enhanced reliability and application-specific operation. Configurable features, optional DMA engines, and other attributes make the cores versatile and effective TSN solutions.
The Result: Demonstrating Flawless Network Time Synchronization
Even when a network cable is intentionally disconnected to break the ring topology, the remaining network nodes stay perfectly synchronized due to built-in redundancy features. Only when a second cable is removed, fully isolating a device, does its signal drift out of sync, clearly proving the TSN synchronization's effectiveness across the connected network.
Getting Started with CAST/Fraunhofer IPMS and Altera
Altera FPGAs, from the Cyclone® V SoC FPGA to the versatile Agilex 3 and Agilex 5 families, provide excellent hardware platforms for deploying deterministic TSN networks today. Customers aiming to implement TSN for demanding industrial, automotive, or avionics applications can leverage the proven, compact, Fraunhofer IPMS IP cores available through CAST.
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