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FPGA-based reference design from Algo-Logic and Intel cuts high-speed financial trading latency by 3.8X

sleibson
Employee
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Algo-Logic and Intel have developed a high-speed reference framework design that offloads the network stack required for high-speed financial trading to logic instantiated in an Intel® Stratix® 10 FPGA on the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) D5005 platform. The reference design includes:

  • A fast PCIe interface (the Algo-Logic Fast Data Mover)

  • A C/C++ to FPGA business logic implementation area that serves as a target for logic developed using high level synthesis (HLS)

  • A TCP/IP offload engine

  • An ultra-low-latency (ULL) 10GbE media access control (MAC)


According to the conclusion in a new White Paper titled “Low-Latency Data Mover Framework from Algo-Logic with Intel® FPGA PAC D5005,” the reference design achieves 3.8X lower latency compared to a design with just an Ethernet offload engine.1 These innovations significantly accelerate low-latency trading system development while offering the flexibility to add proprietary trading algorithms to the FPGA.

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Notices & Disclaimers

1. Testing by Algo-Logic on October 26, 2020. Server configuration: HPE DL380 G10, CPU = Intel® Xeon® Gold processor 6154 @ 3.00 GHz; DRAM = 128 GB total, and RHEL* 7.6. Production Intel FPGA PAC D5005. For more information, a benchmark report is available under NDA. Contact your sales rep for more information.

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