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Free “Ask an Expert” Webinar: Debugging with Signal Tap for Intel® FPGAs, November 3

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Intel® Quartus® Prime Pro Edition Software version 21.3 includes three new innovations for the Signal Tap Logic Analyzer:
• Signal Preservation – allows pre-synthesis node names during debug
• Incremental Signal Tap compilation – faster compilation times when making changes to selected debugs nodes
• Simulator-Aware Signal Tap – extends the visibility of your system by priming your simulator with real-world data taken from an initial Signal Tap capture

Intel is hosting an “Ask an Expert” Webinar on Wednesday, November 3rd at 9:00AM PDT to answer all your Signal Tap Logic Analyzer related questions.

The Signal Tap Logic Analyzer captures and displays the real-time signal behavior of designs instantiated in Intel® FPGAs. It can be used to probe and debug the behavior of internal signals during normal device operation without dedicating I/O pins to the analyzer, without additional external lab equipment. The Analyzer captures data continuously from specified signals based on specified trigger conditions. After capture, the data is available to transfer and display for analysis and debug.
The improvements made to the Signal Tap Logic Analyzer enable novices and experts alike to get their designs to production faster.

Join the Session

Join the upcoming webinar Wednesday, November 3rd, 9:00 to 10:00 am PDT, 17:00 to 18:00 Central European Standard Time and discuss FPGA design debugging techniques live with other designers.

This is not a one-way Webcast. It’s an interactive discussion between an Intel Signal Tap Logic Analyzer expert and your engineering peers. Everyone is welcome to join and ask questions, no matter the level of experience.

This session will be run by Steven Strell, who has been in the Intel FPGA Training group for 14 years. His areas of expertise include hardware design tools found in the Intel® Quartus® Prime software such as Platform Designer and debugging tools like the Signal Tap embedded logic analyzer. Get answers to your burning FPGA design questions including troubleshooting and debugging help using the Signal Tap analyzer for Intel FPGAs.

Register for Debugging with Signal Tap for Intel FPGAs Ask an Expert Webinar and Submit any questions you may have regarding the Signal Tap Logic Analyzer for Intel FPGAs.
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Program Manager, PSG Marketing