Are you curious about debugging with the Signal Tap logic analyzer and some of the new innovations such as Signal Preservation, Incremental Signal Tap compilation, and Simulator-Aware Signal Tap? Intel is holding an "Ask an Expert Webinar" on Tuesday, June 27 at 9:00 AM PDT to answer your questions about the Signal Tap logic analyzer and the latest innovations.
The Signal Tap logic analyzer captures and displays the real-time signal behavior of designs instantiated in Intel® FPGAs. You can use the Signal Tap logic analyzer to probe and debug the behavior of internal signals during normal device operation without dedicating I/O pins to the analyzer and without needing external lab equipment. The Signal Tap logic analyzer captures data continuously from specified signals based on specified trigger conditions that start and stop data capture. After capture, the data is available to transfer and display for analysis and debugging. Signal Preservation allows you to use your pre-synthesis node names when choosing nodes to debug. Incremental Signal Tap compilation provides significantly improved compilation times when making changes to chosen debug nodes. The Simulator-Aware Signal Tap allows you to extend the visibility of your system by priming your simulator with real-world data taken from an initial Signal Tap capture. With the Signal Tap logic analyzer, including these recent productivity innovations, novices and experts can use Signal Tap to get their designs to production faster.
During the upcoming “Ask an Expert / Webinar” event (Tuesday, June 27th 9:00 to 10:00 am PDT, 17:00 to 18:00 Central European Standard Time) you can ask questions and discuss FPGA design debugging techniques with other designers. This is not a one-way Webcast. It’s an interactive discussion with an Intel Signal Tap logic analyzer expert and your engineering peers. No matter what level of experience you have, everyone is welcome to come and ask questions.
This “Ask an Expert / Webinar” session will be run by Steven Strell, who has been in the Intel FPGA Training group for 16 years. His specialty areas include the hardware design tools found in the Intel® Quartus® Prime Software, such as the Platform Designer, and debugging tools like the Signal Tap embedded logic analyzer. Come and ask Steve your burning questions about FPGA-based design troubleshooting and debugging using the Signal Tap logic analyzer for Intel FPGAs.
Register here.
