This week at the Intel Innovation event held in Silicon Valley, Intel previewed a new family of Intel® Agilex™ FPGAs and SoCs (code named Sundance Mesa) that takes many of the innovations of earlier Intel Agilex device families to deliver power-efficient performance for edge, embedded, and network applications.
These advances provide smaller form factor and power-optimization features that suit a variety of applications, including workloads in industrial, broadcast, automotive, communications, consumer, test and measurement, and medical markets. This new family provides lower levels of power consumption and smaller form factors by using Intel 7 technology, monolithic device construction, and several new architectural features.
The new Intel Agilex device family inherits many of the most important architectural features of earlier Intel Agilex devices including the second-generation Intel® Hyperflex™ FPGA Architecture, which places Hyper-Registers throughout the FPGA. These registers allow the Intel® Quartus® Prime Software to maximize performance and minimize power consumption of designs instantiated in the Intel Agilex FPGA logic fabric.
The architectural design of this new Intel Agilex FPGA and SoC family delivers adaptable and scalable capabilities. These devices combine the power-efficient Intel Agilex FPGA fabric with a broad set of intellectual property (IP) and connectivity options including high-speed transceivers that support data rates to 28.1 Gbps and the PCIe 4.0 interface protocol.
The new Intel Agilex device family also supports DDR4, LPDDR4, DDR5, and LPDDR5 SDRAM; general purpose I/O with output voltages ranging from 1.05 V to 3.3 V; in addition a hard processor system (HPS) based on a multi-core Arm Cortex CPU with two Arm Cortex-A76 processor cores that can run as fast as 1.8 GHz and two Arm Cortex-A55 processor cores that can run as fast as 1.5 GHz. The processor cores can be coupled using Arm DynamIQ technology, which combines the Arm Cortex-A76 and Arm Cortex-A55 CPUs into the first asymmetric Arm application processor cluster in an FPGA to deliver improved power and performance for edge applications.
In addition, customers can implement reliable and secure systems with functional safety (FuSa) and an integrated security device manager (SDM) offering advanced security features in a single device family.
The Enhanced Digital Signal Processing (DSP) with AI Tensor Block within the FPGA fabric of these new Intel Agilex FPGAs and SoCs inherit the design of the variable-precision DSP blocks in the earlier Intel Agilex device families, which already offer AI capabilities. In addition, it adds features derived from the tensor block used in the Intel® Stratix® 10 NX FPGAs. The Enhanced DSP with AI Tensor Block introduces two new important operations: the tensor processing capability for AI and complex number support for signal processing applications such as FFTs and complex FIR filters.
The first mode enhances AI with the INT8 tensor mode, which provides twenty INT8 multiplications within one Enhanced DSP with AI Tensor Block, and increases INT8 compute density by 5x versus earlier Intel Agilex device families. The tensor mode uses a two-column tensor structure with both INT32 and FP32 cascade and accumulation capability, and also supports a block floating exponent for improved inference accuracy and low-precision training. In addition, the AI capability of the variable precision DSP functionality has also been enhanced. The vector mode has been upgraded from four INT9 multipliers to six INT9 multipliers. These modes are extremely useful for AI-centric tensor math and for various DSP applications.
The second new mode, the complex-number operation, doubles the performances of the tensor block when performing complex-number multiplication. Previously, two DSP blocks were needed for complex-number multiplication, but this new family of Intel Agilex FPGAs and SoCs can multiply 16-bit, fixed-point, complex numbers within one Enhanced DSP with AI Tensor Block.
Intel’s software tools will enable ease of use to optimize the power and area footprint of AI resources. This is the FPGA industry’s only single push-button-flow, incorporating AI frameworks (such as TensorFlow and PyTorch) for specific throughput and latency targets and creating custom-sized inference IP.
Since a major focus for this product family is to support the industrial, and video imaging markets several hardened connectivity interfaces were added to the feature set. The Time Sensitive Network (TSN) controller to support deterministic latency requirements for industrial networks and the MIPI Phy interface to support the increasing bandwidth requirements for interfacing with the latest image sensors.
Fabricated with Intel 7 technology, these new Intel Agilex FPGAs and SoCs can either operate their core voltage in fixed mode of 0.75v or variable, tuned mode using Intel SmartVID, which further lowers total power consumption. In addition, the members of this Intel FPGA and SoC family implement power islands and power gating.
With all these architectural and process innovations, this new family of Intel Agilex FPGAs and SoCs can lower overall power consumption while achieving higher performance when compared to previous generations of FPGAs. This results in as much as a 1.6x better performance per watt compared to competing 16nm FPGAs.
Furthermore, by leveraging Intel’s advanced manufacturing capabilities for supply resiliency, customers can expect best-in-class lead times for a predictable supply chain. Intel is offering an extra incentive to the engineering community to try these new devices out by providing access to the complete device family in Quartus Pro free of charge.
Contact sales to learn more about the new family of Intel Agilex FPGAs and SoCs.
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