FPGA
Connect with Intel® experts on FPGAs and Programmable Solutions
212 Discussions

Intel® Quartus® Prime Software 23.1 sports new features and IP including a new RISC-V proces

Joel_Aaron_Seely
Employee
0 0 2,489

The Intel® Quartus® Prime Software v23.1 is now available for download. This new software version comes packed with many new features and intellectual property (IP) to make designing systems based on Intel® FPGAs easier than ever. This software version supports Intel Agilex® FPGAs and SoCs M-Series.

Feature additions to the Intel Quartus software IP library include:

  • The Nios® V/g general-purpose processor core, based on the RISC-V RV32IMA instruction set architecture
  • A debug toolkit with Lane Margin support for PCI Express 5.0 for Intel Agilex devices that incorporate R tiles
  • Support for Compute Express Link (CXL) 1.1 with base hard IP and a cache-line state tracker for Intel Agilex devices that incorporate R tiles
  • DDR5 and LPDDR5 SDRAM interfaces for Intel Agilex® 7 FPGAs M-Series
  • HBM2e in-package DRAM support for Intel Agilex 7 FPGAs M-Series
  • A JESD204C interface that supports data rates 32.44 Gbps for Intel Agilex devices that incorporate F tiles
  • A system-level design example showing the MACsec and accompanying cryptographic IP in a 25G/100G full duplex implementation
  • HDMI 2.1 pixel duplication/deduplication support for Intel Agilex 7 FPGAs M-Series
  • DisplayPort: DP1.4 HDCP support for Intel Agilex 7 FPGAs
  • DisplayPort 2.0 UHBR10 + HDCP support for Intel Agilex 7 FPGAs
  • 12G-SDI support for Intel Agilex 7 FPGAs M-Series

The Nios V/g core is the second soft processor core in the Nios® V embedded processor series and is supported in Intel Agilex, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX FPGAs and SoCs. The Nios V/g processor core is based on the RISC-V RV32IMA instruction set architecture and delivers more capabilities and better performance over the existing Nios V/m core, with hardware features including:

  • Configurable instruction/data caches (1, 2, 4, 8, or 16 Kilobytes each)​
  • An integer multiply/divide unit
  • Atomic read-modify-write instructions
  • Support for user-defined custom instructions

In addition, the Nios V/g core has an expanded software ecosystem including FreeRTOS, and Zephyr RTOS support. The Ashling RiscFree IDE is also enhanced with debug support for FreeRTOS and Zephyr RTOS in addition to the existing support for the Intel Hardware Abstraction Layer (HAL) and uCOS operating system. Nios V/g is currently supported on the Intel Agilex, Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices.

Additions to the Intel Quartus Prime Software tools include a revamped design netlist infrastructure (DNI), which is a new backend database that allows faster compilation speeds with improved features. Three new features built upon this new DNI include a new RTL Analyzer, Synopsys Design Constraints (SDC) for register transfer level (RTL), and Post-Synthesis Static Timing Analysis.

The new RTL Analyzer incorporates several added features including:

  • An object constraints viewer that allows you to cross-probe an assignment or constraint to the source file
  • An object set console for easier object visualization of object by list, hierarchy, or type
  • A sweep hints viewer that displays the reasons that objects were removed during synthesis

The SDC for RTL feature allows you to attach timing constraints to RTL names instead of post-synthesis netlist names. This feature speeds the process of constraining the design because the designer can use the names assigned to nodes in a design instead of needing to figure out the new node name following synthesis.

Post-Synthesis Static Timing Analysis helps to estimate the final design timing without a full compilation, reducing the duration of this task from hours to minutes.  This feature helps to identify issues that will affect timing closure earlier in the design cycle.

Additional Intel Quartus Prime Software features include:

  • Parameterizable macros for memory and FIFOs, which allow faster compilation when changing the configuration of external memory interfaces or FIFO IP.
  • Enhanced fixed-point DSP register packing summary and fixed-point DSP register packing details reports, which now include additional information including register names, register usage (fully registered, partially registered, or unregistered), and the reasons that prevent register packing.
  • A new Exploration Dashboard that aggregates and compares compilation results from multiple projects to determine the best implementation.

The Intel Quartus Prime Software v23.1 is available for download now. For more information, view the web page.