Last year at Architecture Day 2021, Intel introduced a new product category–the Infrastructure Processing Unit (IPU)–to accelerate datacenter network infrastructure. This year at Intel Vision 2022, the company unveiled an IPU roadmap stretching through 2025 and beyond. This announcement was made during the keynote and further detailed in two sessions: “Datacenter of the Future: Efficient, Secure, and Sustainable” on Day 1 and “How Software Defined & Programmable Platforms Will Fuel Your Innovation” on Day 2. During the “Datacenter of the Future session,” Deepali Trehan, VP of Datacenter and AI and General Manager of Intel Programmable Solutions Group Product Marketing at Intel, reviewed current Intel IPU offerings and then presented this IPU road map:
Today, Intel offers two second-generation 200G programmable IPUs: Oak Springs Canyon and Mount Evans. Oak Springs Canyon is based on an Intel® Xeon® D processor and an Intel® Agilex™ FPGA. Mount Evans is Intel’s first ASIC-based IPU, which was designed in collaboration with Google for the Google Cloud Platform. Both the Oak Springs Canyon and Mount Evans IPUs deliver the infrastructure acceleration needed to offload 200G workloads and both IPUs work in concert with servers based on Intel Xeon CPUs.
The Mount Evans IPU is based on a best-in-class packet-processing engine, instantiated in an ASIC. This ASIC supports many networking use cases–including vSwitch offload, firewalls, and virtual routing–and provides significant headroom for future use cases. The Mount Evans IPU emulates NVMe devices at very high IOPS rates by leveraging and extending the Intel® Optane™ NVMe controller.
Trehan explained why Intel offers both ASIC- and FPGA-based IPUs. ASIC-based IPUs deliver optimized performance and power, used for secure networking and storage tasks. FPGA-based IPUs deliver faster time to market for evolving network standards, provide a reprogrammable and secure datapath, and can more flexibly handle many types of custom workloads. Both Oak Springs Canyon and Mount Evans are supported by a common programming model called IPDK (Infrastructure Programmer Development Kit), which is an open source, vendor agnostic framework of drivers and APIs for infrastructure offload and management that runs on many hardware platforms including CPUs and IPUs.
At the beginning of her part of the session, Trehan presented a short video made by Derek Chiou, a Partner Hardware Architect for next-generation datacenter architecture at Microsoft. He explained that Microsoft had designed in and deployed millions of Intel FPGAs in its worldwide network of datacenters, demonstrating Microsoft’s substantial experience in using FPGAs for datacenter infrastructure acceleration. Chiou then said that FPGA-based acceleration has resulted in a 5X latency reduction for Microsoft’s Azure customers and that he believes that FPGA-based IPUs will deliver similar results.
Trehan then described the next step in the Intel IPU roadmap. In the next two to three years, Intel will introduce the next-generation versions of the FPGA-based Oak Springs Canyon and ASIC-based Mount Evans IPUs, code named Hot Springs Canyon and Mount Morgan respectively. These next-generation IPUs will be 400G IPUs. Sometime after Intel introduces the Hot Springs Canyon and Mount Morgan 400G IPUs, during 2025 or later, Intel will roll out a new generation of 800G FPGA- and ASIC-based IPUs.
Intel believes that IPUs are essential to the Datacenter of the Future’s success because IPUs reduce the infrastructure overhead that bogs server CPUs down. Trehan said that there are more than seven million datacenters worldwide, ranging from Cloud datacenters down to on-premise, edge-based datacenters, and all of these datacenters have infrastructure bottlenecks. IPUs can relieve many of these infrastructure bottlenecks by freeing up server CPUs to run application workloads instead of infrastructure tasks, as illustrated by this graphic:
During the Software Defined and Programmable Platforms session on Intel Vision 2022 Day 2, Sachin Katti, Chief Technology Officer, Network & Edge Group (NEX), Intel, described how Intel’s strategy and technology allow the company to arm its customers with the capabilities they need to transform their datacenters and edge deployments. Intel IPUs are already a key part of the Intelligent Fabric offering in datacenters and primarily target the needs of cloud service providers (CSPs), but communications service providers (CoSPs) and large enterprises are reaping the benefits of IPUs in their datacenters as well. Intel IPUs improve security, reduce overhead, and free up CPUs to run business workloads by isolating the service provider’s infrastructure workloads from the workloads being run by their datacenter tenants.
Katti also described how Intel’s IPUs are enabled by a powerful open-source software foundation, including the vendor-agnostic IPDK, which builds upon Intel’s history of working with the open-source community–on projects such as SPDK, DPDK, and P4–simplify the development of leading-edge software and services. IPDK allows developers to focus on their applications instead of the underlying API or complexities of the hardware. With this IPU roadmap, said Katti, Intel continues to deliver on its commitments to better serve customer needs with improved datacenter efficiency and manageability by helping its partners and customers create open software ecosystems and end-to-end programmable networks.
IPUs deliver multiple benefits to the datacenter including superior TCO, improved performance, improved power efficiency, reduced latency, and improved security. As a result, CSPs along with CoSPs, enterprise customers, and customers in many other market segments are already widely adopting Intel IPUs, which is why Intel has now extended its public IPU road map by two more generations.
To watch Derek Chiou’s 90 second testimonial “Optimizing Microsoft Data Center Networking with Intel FPGAs," click here.
For more information about Intel Infrastructure Processing Units and SmartNICs, click here.
Sabrina is Director of Marketing, FPGA Platforms and has over 20 years of experience serving a wide breadth of markets including data center, communications and industrial with a strong technical background in FPGAs. She has a Bachelor of Science degree in Electrical Engineering from San Jose State University.